公开(公告)号：US20230031546A1

公开(公告)日：2023-02-02

申请号：US17691438

申请日：2022-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Mo PARK ,  Yeon Ho PARK ,  Wang Seop LIM

IPC: H01L29/423 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238

Abstract: There is provided a semiconductor device capable of improving the performance and reliability of a device. The semiconductor device including an active pattern extending in a first direction, a gate structure on the active pattern, the gate structure extending in a second direction different from the first direction and including a gate insulating layer and a gate filling layer, a gate spacer extending in the second direction, on a sidewall of the gate structure, a gate shield insulating pattern on a sidewall of the gate spacer, covering an upper surface of the gate insulating layer, and including an insulating material, and a gate capping pattern covering an upper surface of the gate filling layer, on the gate structure may be provided.

公开(公告)号：US20250151382A1

公开(公告)日：2025-05-08

申请号：US18663258

申请日：2024-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye In CHUNG ,  Dong-Gwan SHIN ,  Yeon Ho PARK ,  Yong Hee PARK ,  Hong Seon YANG

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

Abstract: A semiconductor device includes a first gate isolation structure. A second gate isolation structure is spaced apart from the first gate isolation structure in a first direction. A first active pattern is disposed between the first and second gate isolation structures. The first active pattern extends longitudinally in a second direction crossing the first direction. A second active pattern is disposed between the first and second gate isolation structures. The second active pattern extends longitudinally in the second direction and is spaced apart from the first active pattern in the first direction. Gate structures are disposed between the first and second gate isolation structures. The gate structures directly contact the first and second gate isolation structures. A length of the first gate isolation structure in the second direction is greater than a length of the second gate isolation structure in the second direction.

公开(公告)号：US20230086174A1

公开(公告)日：2023-03-23

申请号：US17852658

申请日：2022-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Mo PARK ,  Yeon Ho PARK ,  Eun Sil PARK ,  Jin Seok LEE ,  Wang Seop LIM ,  Kyu Bong CHOI

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/775 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/66

Abstract: A semiconductor device includes first and second sheet patterns spaced apart from each other on a first region of the substrate, a first gate electrode extending between the first and second sheet patterns, third and fourth sheet patterns spaced apart from each other on a second region of the substrate, and a second gate electrode extending between the third and fourth sheet patterns. The first gate electrode includes a first work function controlling film, which is between the first and second sheet patterns, and a first filling conductive film on the first work function controlling film. The second gate electrode includes a second work function controlling film, which is between the third and fourth sheet patterns, and a second filling conductive film on the second work function controlling film. A distance between the third and fourth sheet patterns is greater than a distance between the first and second sheet patterns.

公开(公告)号：US20230040132A1

公开(公告)日：2023-02-09

申请号：US17741711

申请日：2022-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Mo PARK ,  Kyu Bong CHOI ,  Yeon Ho PARK ,  Eun Sil PARK ,  Jin Seok LEE ,  Wang Seop LIM ,  Kyung In CHOI

IPC: H01L21/02 ,  H01L21/8234 ,  H01L21/768

Abstract: A method of manufacturing a semiconductor device includes: forming first to third preliminary active patterns on a substrate to have different intervals therebetween, forming first and second field insulating layers between the first and second preliminary active patterns and between the second and third preliminary active patterns, respectively, and forming first to third gate electrodes respectively on first to third active patterns formed based on the first to third preliminary active patterns, separated by first and second gate isolation structures.