公开(公告)号：US20180260019A1

公开(公告)日：2018-09-13

申请号：US15916794

申请日：2018-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Seok KIM ,  Yong Seung Yi ,  Du Hyun KIM ,  Yong Jae LEE ,  Ho Yeong LIM ,  Byeong Bae HYEON ,  Dong Il SON

IPC: G06F1/32 ,  H02J7/00 ,  G01R31/36

Abstract: An electronic device includes a power management circuit which supplies power from a battery to electronic components, a battery management circuit which controls connection between the battery and the power management circuit, a physical key formed on a part of the electronic device, a key control circuit which controls connection between the physical key and the battery management circuit, and a processor connected to the power management circuit. The processor is configured to transmit a signal for powering off the electronic device to the power management circuit, and when the electronic device is powered off, to control the key control circuit to connect the physical key with the battery management circuit. The power management circuit is configured to, when receiving the signal for powering off the electronic device, control the battery management circuit to disconnect the battery from the one or more electronic components included in the electronic device.

公开(公告)号：US20230354615A1

公开(公告)日：2023-11-02

申请号：US18104882

申请日：2023-02-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Jae LEE ,  Seul Ji SONG

IPC: H10B63/00 ,  H10N70/00

CPC classification number: H10B63/24 ,  H10B63/84 ,  H10N70/841

Abstract: A semiconductor memory device includes a substrate, a first electrode on the substrate, a second electrode on the first electrode, an OTS film between the first electrode and the second electrode, and an electrode spacer film disposed on a part of a side wall of the OTS film, wherein the OTS film includes a first surface that is in contact with the first electrode, a second surface that is in contact with the second electrode, and a third surface that is in contact with the electrode spacer film, and a logical state of data stored in the OTS film is based on polarity of a program voltage.

公开(公告)号：US20230114539A1

公开(公告)日：2023-04-13

申请号：US17845274

申请日：2022-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong Jae LEE ,  Jihun BYUN

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: A variable resistance memory device includes active regions apart from each other, common bit line contacts in the active regions, first active source contacts on first active regions near one edge of each of the common bit line contacts, second active source contacts on second active regions near another edge of each of the common bit line contacts, word lines between the first active source contacts and the common bit line contacts and between the common bit line contacts and the second active source contacts, bit lines on the common bit line contacts, variable resistance layers connected to the second active source contacts, the word lines, and the bit lines, spin-orbit torque (SOT) layers connected to the first active source contacts on the variable resistance layers, the word lines, and the bit lines, source line contacts on the SOT layers, and source lines connected to the source line contacts.