公开(公告)号：US09034765B2

公开(公告)日：2015-05-19

申请号：US13956556

申请日：2013-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonsoo Park ,  JungWoo Seo ,  KyoungRyul Yoon ,  Cheolhong Kim ,  Seokwoo Nam ,  Yongjik Park

IPC: H01L21/311 ,  H01L21/302

CPC classification number: H01L21/302 ,  H01L21/0337

Abstract: A method of forming a semiconductor device includes first preliminary holes over an etch target, the first preliminary holes arranged as a plurality of rows in a first direction, forming dielectric patterns each filling one of the first preliminary holes, sequentially forming a barrier layer and a sacrificial layer on the dielectric patterns, forming etch control patterns between the dielectric patterns, forming second preliminary holes by etching the sacrificial layer, each of the second preliminary holes being in a region defined by at least three dielectric patterns adjacent to each other, and etching the etch target layer corresponding to positions of the first and second preliminary holes to form contact holes.

Abstract translation: 形成半导体器件的方法包括在蚀刻靶上的第一预备孔，第一预备孔在第一方向上排列成多行，形成各自填充一个第一预备孔的电介质图案，依次形成阻挡层和 在电介质图案上形成牺牲层，在电介质图案之间形成蚀刻控制图案，通过蚀刻牺牲层形成第二预备孔，每个第二预备孔位于由彼此相邻的至少三个电介质图案限定的区域中，以及蚀刻 所述蚀刻目标层对应于所述第一和第二预备孔的位置以形成接触孔。