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    METHODS OF REVISING OVERLAY CORRECTION DATA
    1.
    发明申请
    METHODS OF REVISING OVERLAY CORRECTION DATA 有权
    修改覆盖数据的方法

    公开(公告)号：US20160351455A1

    公开(公告)日：2016-12-01

    申请号：US15001729

    申请日：2016-01-20

    申请人： Samsung Electronics Co., Ltd.

    发明人： Woojin Jung ,  Sang-Ho Yun ,  Un Jeon ,  Byeongsoo Kim ,  Cheolhong Kim ,  Taehong Min ,  Joonsoo Park

    IPC分类号： H01L21/66 ,  G01N21/95 ,  G01B11/00 ,  H01L21/027 ,  G01B11/27

    CPC分类号： H01L22/12 ,  G01B11/002 ,  G01B11/272 ,  G03F7/70633 ,  H01L21/0274

    摘要： Provided are methods of generating and revising overlay correction data, a method of performing a photolithography process using the overlay correction data, and a method of performing a photolithography process while revising the overlay correction data. The method of revising the overlay correction data includes forming a plurality of overlay keys on a first set of wafers using first overlay correction data, measuring first overlay keys formed on first overlay coordinates in a first shot area of a first wafer among the first set of wafers, generating first overlay error data, and revising primarily the first overlay correction data using the first overlay error data, measuring second overlay keys formed on second overlay coordinates in a second shot area of a second wafer among the first set of wafers, generating second overlay error data, and revising secondarily the primarily revised first overlay correction data using the second overlay error data, and measuring third overlay keys formed on third overlay coordinates in a third shot area of a third wafer among the first set of wafers, generating third overlay error data, revising tertiarily the secondarily revised first overlay correction data, and generating second overlay correction data. The first overlay coordinates, the second overlay coordinates, and the third overlay coordinates are mutually exclusive.

    摘要翻译： 提供了生成和修改覆盖校正数据的方法，使用覆盖校正数据执行光刻处理的方法，以及在修改覆盖校正数据的同时执行光刻处理的方法。 修改覆盖校正数据的方法包括使用第一覆盖校正数据在第一组晶片上形成多个覆盖键，测量在第一组中的第一晶片的第一覆盖坐标中形成的第一覆盖坐标， 生成第一重叠错误数据，并且使用第一重叠错误数据主要修改第一重叠校正数据，测量形成在第一组晶片中的第二晶片的第二拍摄区域中的第二覆盖坐标上的第二重叠键，产生第二叠加错误数据 重叠错误数据，并且使用第二覆盖误差数据二次修改主要修改的第一覆盖校正数据，以及测量形成在第一晶片组中的第三晶片的第三拍摄区域中的第三覆盖坐标上的第三覆盖键，生成第三覆盖 错误数据，二次修改二次修改的第一重叠校正数据，并产生第二叠加校正 数据。 第一覆盖坐标，第二覆盖坐标和第三覆盖坐标是相互排斥的。

    Method of fabricating semiconductor device
    2.
    发明授权
    Method of fabricating semiconductor device 有权

    公开(公告)号：US10096603B2

    公开(公告)日：2018-10-09

    申请号：US15230585

    申请日：2016-08-08

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Heejung Kim ,  Seok-Won Cho ,  Joonsoo Park ,  SoonMok Ha

    IPC分类号： H01L27/108 ,  H01L27/11582 ,  H01L49/02

    摘要： A method of fabricating a semiconductor device includes forming first cell patterns on a substrate, forming a first layer relative to the first cell patterns, and forming a second cell pattern and a peripheral pattern on the first layer. The second cell pattern includes first holes in a cell region and the peripheral pattern is located in a peripheral region. The method also includes filling the first holes, removing the second cell pattern to expose pillars, and forming second holes. Each of the second holes corresponds to adjacent cell spacers of the pillars. The method also includes removing the pillars to form third holes corresponding to respective ones of the cell spacers, and etching the substrate using the cell spacers, the first cell patterns, and the peripheral pattern as etch masks to form a trench.

    Methods of revising overlay correction data
    5.
    发明授权
    Methods of revising overlay correction data 有权

    公开(公告)号：US09679821B2

    公开(公告)日：2017-06-13

    申请号：US15001729

    申请日：2016-01-20

    申请人： Samsung Electronics Co., Ltd.

    发明人： Woojin Jung ,  Sang-Ho Yun ,  Un Jeon ,  Byeongsoo Kim ,  Cheolhong Kim ,  Taehong Min ,  Joonsoo Park

    IPC分类号： H01L21/66 ,  H01L21/027 ,  G01B11/27 ,  G01B11/00 ,  G03F7/20

    CPC分类号： H01L22/12 ,  G01B11/002 ,  G01B11/272 ,  G03F7/70633 ,  H01L21/0274

    摘要： Provided are methods of generating and revising overlay correction data, a method of performing a photolithography process using the overlay correction data, and a method of performing a photolithography process while revising the overlay correction data. The method of revising the overlay correction data includes forming a plurality of overlay keys on a first set of wafers using first overlay correction data, measuring first overlay keys formed on first overlay coordinates in a first shot area of a first wafer among the first set of wafers, generating first overlay error data, and revising primarily the first overlay correction data using the first overlay error data, measuring second overlay keys formed on second overlay coordinates in a second shot area of a second wafer among the first set of wafers, generating second overlay error data, and revising secondarily the primarily revised first overlay correction data using the second overlay error data, and measuring third overlay keys formed on third overlay coordinates in a third shot area of a third wafer among the first set of wafers, generating third overlay error data, revising tertiarily the secondarily revised first overlay correction data, and generating second overlay correction data. The first overlay coordinates, the second overlay coordinates, and the third overlay coordinates are mutually exclusive.

    SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME 有权

    公开(公告)号：US20170103987A1

    公开(公告)日：2017-04-13

    申请号：US15237709

    申请日：2016-08-16

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jaehee Kim ,  Soonmok Ha ,  Jonghyuk Kim ,  Joonsoo Park

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10894 ,  H01L27/10814 ,  H01L27/10826 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10879 ,  H01L27/10885 ,  H01L28/90

    摘要： A method for manufacturing a semiconductor device includes forming first and second lower structures including selection elements on first and second chip regions of a substrate, respectively, forming first and second mold layers on the first and second lower structures, respectively, forming first and second support layers on the first and second mold layers, respectively, patterning the first support layer and the first mold layer to form first holes exposing the first lower structure, forming first lower electrodes in the first holes, forming a support pattern including at least one opening by selectively patterning the first support layer while leaving the second support layer, and removing the first mold layer through the opening. A top surface of the support pattern is disposed at a substantially same level as a top surface of the second support layer.

    Methods of forming fine patterns for semiconductor devices
    8.
    发明授权
    Methods of forming fine patterns for semiconductor devices 有权
    形成半导体器件精细图案的方法

    公开(公告)号：US09099399B2

    公开(公告)日：2015-08-04

    申请号：US14467400

    申请日：2014-08-25

    申请人： Samsung Electronics Co., Ltd.

    发明人： Joonsoo Park ,  Soonmok Ha ,  Eunshoo Han ,  Seongho Moon ,  Sung-Wook Hwang

    IPC分类号： H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311

    CPC分类号： H01L21/30604 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/10852 ,  H01L27/11551 ,  H01L27/11578

    摘要： Methods of forming fine patterns for semiconductor devices are provided. A method may include sequentially forming a lower layer and a mask layer having first openings on a substrate, forming pillars to fill the first openings and protrude upward from a top surface of the mask layer, forming a block copolymer layer on the substrate with the pillars, performing a thermal treatment to the block copolymer layer to form a first block portion and second block portions, removing the second block portions to form guide openings exposing the mask layer, and etching the mask layer exposed by the guide openings to form second openings.

    摘要翻译： 提供了形成用于半导体器件的精细图案的方法。 一种方法可以包括顺序地形成下层和在衬底上具有第一开口的掩模层，形成柱以填充第一开口并从掩模层的顶表面向上突出，在衬底上形成具有柱的嵌段共聚物层 对所述嵌段共聚物层进行热处理以形成第一嵌段部分和第二嵌段部分，除去所述第二嵌段部分以形成暴露所述掩模层的引导开口，以及蚀刻由所述引导开口露出的掩模层以形成第二开口。

    Methods of forming a semiconductor device
    9.
    发明授权
    Methods of forming a semiconductor device 有权
    形成半导体器件的方法

    公开(公告)号：US09034765B2

    公开(公告)日：2015-05-19

    申请号：US13956556

    申请日：2013-08-01

    申请人： Samsung Electronics Co., Ltd.

    发明人： Joonsoo Park ,  JungWoo Seo ,  KyoungRyul Yoon ,  Cheolhong Kim ,  Seokwoo Nam ,  Yongjik Park

    IPC分类号： H01L21/311 ,  H01L21/302

    CPC分类号： H01L21/302 ,  H01L21/0337

    摘要： A method of forming a semiconductor device includes first preliminary holes over an etch target, the first preliminary holes arranged as a plurality of rows in a first direction, forming dielectric patterns each filling one of the first preliminary holes, sequentially forming a barrier layer and a sacrificial layer on the dielectric patterns, forming etch control patterns between the dielectric patterns, forming second preliminary holes by etching the sacrificial layer, each of the second preliminary holes being in a region defined by at least three dielectric patterns adjacent to each other, and etching the etch target layer corresponding to positions of the first and second preliminary holes to form contact holes.

    摘要翻译： 形成半导体器件的方法包括在蚀刻靶上的第一预备孔，第一预备孔在第一方向上排列成多行，形成各自填充一个第一预备孔的电介质图案，依次形成阻挡层和 在电介质图案上形成牺牲层，在电介质图案之间形成蚀刻控制图案，通过蚀刻牺牲层形成第二预备孔，每个第二预备孔位于由彼此相邻的至少三个电介质图案限定的区域中，以及蚀刻 所述蚀刻目标层对应于所述第一和第二预备孔的位置以形成接触孔。