公开(公告)号：US09679821B2

公开(公告)日：2017-06-13

申请号：US15001729

申请日：2016-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woojin Jung ,  Sang-Ho Yun ,  Un Jeon ,  Byeongsoo Kim ,  Cheolhong Kim ,  Taehong Min ,  Joonsoo Park

IPC: H01L21/66 ,  H01L21/027 ,  G01B11/27 ,  G01B11/00 ,  G03F7/20

CPC classification number: H01L22/12 ,  G01B11/002 ,  G01B11/272 ,  G03F7/70633 ,  H01L21/0274

Abstract: Provided are methods of generating and revising overlay correction data, a method of performing a photolithography process using the overlay correction data, and a method of performing a photolithography process while revising the overlay correction data. The method of revising the overlay correction data includes forming a plurality of overlay keys on a first set of wafers using first overlay correction data, measuring first overlay keys formed on first overlay coordinates in a first shot area of a first wafer among the first set of wafers, generating first overlay error data, and revising primarily the first overlay correction data using the first overlay error data, measuring second overlay keys formed on second overlay coordinates in a second shot area of a second wafer among the first set of wafers, generating second overlay error data, and revising secondarily the primarily revised first overlay correction data using the second overlay error data, and measuring third overlay keys formed on third overlay coordinates in a third shot area of a third wafer among the first set of wafers, generating third overlay error data, revising tertiarily the secondarily revised first overlay correction data, and generating second overlay correction data. The first overlay coordinates, the second overlay coordinates, and the third overlay coordinates are mutually exclusive.

公开(公告)号：US08785319B2

公开(公告)日：2014-07-22

申请号：US13799125

申请日：2013-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon-Soo Park ,  Kukhan Yoon ,  Joon Kim ,  Cheolhong Kim ,  Seokwoo Nam

IPC: H01L21/4763

CPC classification number: H01L21/3083 ,  H01L21/0331 ,  H01L21/0337 ,  H01L21/31144 ,  H01L27/10817 ,  H01L27/10891 ,  H01L27/11556 ,  H01L27/24 ,  H01L28/91

Abstract: Methods of forming fine patterns are provided. The methods may include forming first hard mask patterns extending in a first direction on a lower layer, forming second hard mask patterns filling gap regions between the first hard mask patterns, forming first mask patterns extending in a second direction perpendicular to the first direction on the first and second hard mask patterns, etching the first hard mask patterns using the first mask patterns as etch masks to form first openings, forming second mask patterns filling the first openings and extending in the second direction, and etching the second hard mask patterns using the second mask patterns as etch masks to form second openings spaced apart from the first openings in a diagonal direction with respect to the first direction.

Abstract translation: 提供形成精细图案的方法。 所述方法可以包括形成在下层上沿着第一方向延伸的第一硬掩模图案，形成填充第一硬掩模图案之间的间隙区域的第二硬掩模图案，形成沿垂直于第一方向的第二方向延伸的第一掩模图案 第一和第二硬掩模图案，使用第一掩模图案蚀刻第一硬掩模图案作为蚀刻掩模以形成第一开口，形成填充第一开口并在第二方向上延伸的第二掩模图案，以及使用 第二掩模图案作为蚀刻掩模，以在相对于第一方向的对角线方向上形成与第一开口间隔开的第二开口。

公开(公告)号：US09034765B2

公开(公告)日：2015-05-19

申请号：US13956556

申请日：2013-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonsoo Park ,  JungWoo Seo ,  KyoungRyul Yoon ,  Cheolhong Kim ,  Seokwoo Nam ,  Yongjik Park

IPC: H01L21/311 ,  H01L21/302

CPC classification number: H01L21/302 ,  H01L21/0337

Abstract: A method of forming a semiconductor device includes first preliminary holes over an etch target, the first preliminary holes arranged as a plurality of rows in a first direction, forming dielectric patterns each filling one of the first preliminary holes, sequentially forming a barrier layer and a sacrificial layer on the dielectric patterns, forming etch control patterns between the dielectric patterns, forming second preliminary holes by etching the sacrificial layer, each of the second preliminary holes being in a region defined by at least three dielectric patterns adjacent to each other, and etching the etch target layer corresponding to positions of the first and second preliminary holes to form contact holes.

Abstract translation: 形成半导体器件的方法包括在蚀刻靶上的第一预备孔，第一预备孔在第一方向上排列成多行，形成各自填充一个第一预备孔的电介质图案，依次形成阻挡层和 在电介质图案上形成牺牲层，在电介质图案之间形成蚀刻控制图案，通过蚀刻牺牲层形成第二预备孔，每个第二预备孔位于由彼此相邻的至少三个电介质图案限定的区域中，以及蚀刻 所述蚀刻目标层对应于所述第一和第二预备孔的位置以形成接触孔。

公开(公告)号：US08614148B2

公开(公告)日：2013-12-24

申请号：US13733376

申请日：2013-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon-Soo Park ,  Jongchul Park ,  Cheolhong Kim ,  Seokwoo Nam ,  Kukhan Yoon

IPC: H01L21/02

CPC classification number: H01L21/308 ,  H01L21/0337 ,  H01L27/10852 ,  H01L28/92

Abstract: A method may include forming first hard mask patterns and second hard mask patterns extending in a first direction and repeatedly and alternately arranged on a lower layer, forming third mask patterns extending in a second direction perpendicular to the first direction on the first and second hard mask patterns, etching the first hard mask patterns using the third mask patterns to form first openings, forming filling patterns filling the first openings and gap regions between the third mask patterns, forming spacers on both sidewalls of each of the filling patterns, after removing the third mask patterns, and etching the second hard mask patterns using the filling patterns and the spacers to form second openings.

Abstract translation: 一种方法可以包括形成第一硬掩模图案和在第一方向上延伸并重复并交替地布置在下层上的第一硬掩模图案和第二硬掩模图案，在第一和第二硬掩模上形成沿垂直于第一方向的第二方向延伸的第三掩模图案 使用第三掩模图案蚀刻第一硬掩模图案以形成第一开口，形成填充第一开口和第三掩模图案之间的间隙区域的填充图案，在移除第三掩模图案的每个填充图案的两个侧壁上之后形成间隔物 掩模图案，并且使用填充图案和间隔件蚀刻第二硬掩模图案以形成第二开口。

公开(公告)号：US20160351455A1

公开(公告)日：2016-12-01

申请号：US15001729

申请日：2016-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woojin Jung ,  Sang-Ho Yun ,  Un Jeon ,  Byeongsoo Kim ,  Cheolhong Kim ,  Taehong Min ,  Joonsoo Park

IPC: H01L21/66 ,  G01N21/95 ,  G01B11/00 ,  H01L21/027 ,  G01B11/27

CPC classification number: H01L22/12 ,  G01B11/002 ,  G01B11/272 ,  G03F7/70633 ,  H01L21/0274

Abstract: Provided are methods of generating and revising overlay correction data, a method of performing a photolithography process using the overlay correction data, and a method of performing a photolithography process while revising the overlay correction data. The method of revising the overlay correction data includes forming a plurality of overlay keys on a first set of wafers using first overlay correction data, measuring first overlay keys formed on first overlay coordinates in a first shot area of a first wafer among the first set of wafers, generating first overlay error data, and revising primarily the first overlay correction data using the first overlay error data, measuring second overlay keys formed on second overlay coordinates in a second shot area of a second wafer among the first set of wafers, generating second overlay error data, and revising secondarily the primarily revised first overlay correction data using the second overlay error data, and measuring third overlay keys formed on third overlay coordinates in a third shot area of a third wafer among the first set of wafers, generating third overlay error data, revising tertiarily the secondarily revised first overlay correction data, and generating second overlay correction data. The first overlay coordinates, the second overlay coordinates, and the third overlay coordinates are mutually exclusive.

Abstract translation: 提供了生成和修改覆盖校正数据的方法，使用覆盖校正数据执行光刻处理的方法，以及在修改覆盖校正数据的同时执行光刻处理的方法。 修改覆盖校正数据的方法包括使用第一覆盖校正数据在第一组晶片上形成多个覆盖键，测量在第一组中的第一晶片的第一覆盖坐标中形成的第一覆盖坐标， 生成第一重叠错误数据，并且使用第一重叠错误数据主要修改第一重叠校正数据，测量形成在第一组晶片中的第二晶片的第二拍摄区域中的第二覆盖坐标上的第二重叠键，产生第二叠加错误数据 重叠错误数据，并且使用第二覆盖误差数据二次修改主要修改的第一覆盖校正数据，以及测量形成在第一晶片组中的第三晶片的第三拍摄区域中的第三覆盖坐标上的第三覆盖键，生成第三覆盖 错误数据，二次修改二次修改的第一重叠校正数据，并产生第二叠加校正 数据。 第一覆盖坐标，第二覆盖坐标和第三覆盖坐标是相互排斥的。

公开(公告)号：US20140329379A1

公开(公告)日：2014-11-06

申请号：US14085194

申请日：2013-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul-Ho Kim ,  Cheolhong Kim ,  Chorong Park ,  Jaehan Lee

IPC: H01L21/308 ,  H01L21/283 ,  H01L21/28

CPC classification number: H01L21/283 ,  H01L21/0274 ,  H01L21/0335 ,  H01L21/28008 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76838 ,  H01L27/11548 ,  H01L27/11575 ,  H01L2221/1021

Abstract: A patterning method includes forming a photoresist layer on a processing layer and exposing the photoresist layer using a standing wave/defocusing exposure to produce a photoresist layer having a staircase pattern.

Abstract translation: 图案化方法包括在处理层上形成光致抗蚀剂层，并使用驻波/散焦曝光曝光光致抗蚀剂层，以产生具有阶梯图案的光致抗蚀剂层。