公开(公告)号：US11079824B2

公开(公告)日：2021-08-03

申请号：US16390821

申请日：2019-04-22

Applicant: SanDisk Technologies LLC

Inventor： Nitin Gupta ,  Bhavin Odedara ,  Raghu Voleti

IPC: G06F1/00 ,  G06F11/30 ,  G06F1/28 ,  G05F1/46 ,  G01R19/165

Abstract: Systems and methods for power distribution are disclosed. A system includes a first power domain that supplies current to an integrated circuit at a first voltage level, a second power domain that supplies current to the integrated circuit at a second voltage level, and a current distribution component that is connected to the first power domain and connectable to the second power domain and senses a metric comprising a first current level or a first voltage level drawn from the first power domain, determines whether the metric exceeds a first threshold, and in response to determining that the metric exceeds the first threshold, electrically connects the second power domain to the integrated circuit to supply additional current such that an aggregate current level received by the integrated circuit comprises current from the first power domain and the additional current from the second power domain.

公开(公告)号：US10001797B2

公开(公告)日：2018-06-19

申请号：US15218566

申请日：2016-07-25

Applicant: SanDisk Technologies LLC

Inventor： Srinivasa Rao Sabbineni ,  Bhavin Odedara ,  Jayanth Mysore Thimmaiah

IPC: G05F1/56 ,  G05F1/577 ,  G05F1/595

CPC classification number: G05F1/577 ,  G05F1/595

Abstract: Regulator circuitry may include a plurality of output circuits to generate a plurality of regulated output voltages. The regulator circuitry may include a single operational amplifier and a single feedback loop for regulation, which may reduce space and power consumed by the regulator circuitry. A transconductor and current mirror circuitry may be included to generate the plurality of regulated output voltages based a single operational amplifier output voltage generated with the single operational amplifier and feedback loop.

公开(公告)号：US10129012B2

公开(公告)日：2018-11-13

申请号：US15473067

申请日：2017-03-29

Applicant: SanDisk Technologies LLC

Inventor： Krishnamurthy Dhakshinamurthy ,  Shajith Musaliar Sirajudeen ,  Jayaprakash Naradasi ,  Bhavin Odedara ,  Yosi Pinto ,  Rampraveen Somasundaram ,  Anand Sharma

IPC: H04L7/00

Abstract: A non-source-synchronous system may include a clock-sending device and a clock-receiving device that communicate via a communications bus. The clock-sending device and the clock-receiving device may perform a tuning operation, in which the clock-receiving device sends one or more data signals on one or more data lines of the communications bus to the clock-sending device. The clock-sending device may delay its internal clock signal by an amount based on the one or more data signals. The clock-sending device may then perform sampling of data signals received from the clock-receiving device based on the tuning operation. The tuning operation may be performed in accordance with SDR or DDR, and thus allow for SDR or DDR communication with optimal sampling for systems that do not use a data strobe.

公开(公告)号：US20180083764A1

公开(公告)日：2018-03-22

申请号：US15473067

申请日：2017-03-29

Applicant: SanDisk Technologies LLC

Inventor： Krishnamurthy Dhakshinamurthy ,  Shajith Musaliar Sirajudeen ,  Jayaprakash Naradasi ,  Bhavin Odedara ,  Yosi Pinto ,  Rampraveen Somasundaram ,  Anand Sharma

IPC: H04L7/00

CPC classification number: H04L7/0012 ,  G06F1/12 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0337

Abstract: A non-source-synchronous system may include a clock-sending device and a clock-receiving device that communicate via a communications bus. The clock-sending device and the clock-receiving device may perform a tuning operation, in which the clock-receiving device sends one or more data signals on one or more data lines of the communications bus to the clock-sending device. The clock-sending device may delay its internal clock signal by an amount based on the one or more data signals. The clock-sending device may then perform sampling of data signals received from the clock-receiving device based on the tuning operation. The tuning operation may be performed in accordance with SDR or DDR, and thus allow for SDR or DDR communication with optimal sampling for systems that do not use a data strobe.

公开(公告)号：US20180026646A1

公开(公告)日：2018-01-25

申请号：US15218638

申请日：2016-07-25

Applicant: SanDisk Technologies LLC

Inventor： Bhavin Odedara ,  Srikanth Bojja ,  Jayanth Mysore Thimmaiah ,  Srinivasa Rao Sabbineni

IPC: H03L7/099 ,  H03L7/093 ,  H03B27/00 ,  H03L7/089

CPC classification number: H03L7/099 ,  H03B27/00 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/0995 ,  H03L7/0997 ,  H03L2207/06

Abstract: A phase-locked loop (PLL) circuit may be configured to generate a plurality of oscillating signals based on a single control voltage generated based on a phase difference between an input signal and a feedback signal. One of the plurality of oscillating signals may be used to generate the feedback signal.

公开(公告)号：US20180024581A1

公开(公告)日：2018-01-25

申请号：US15218566

申请日：2016-07-25

Applicant: SanDisk Technologies LLC

Inventor： Srinivasa Rao Sabbineni ,  Bhavin Odedara ,  Jayanth Mysore Thimmaiah

IPC: G05F1/577 ,  G05F1/595

CPC classification number: G05F1/577 ,  G05F1/595

Abstract: Regulator circuitry may include a plurality of output circuits to generate a plurality of regulated output voltages. The regulator circuitry may include a single operational amplifier and a single feedback loop for regulation, which may reduce space and power consumed by the regulator circuitry. A transconductor and current mirror circuitry may be included to generate the plurality of regulated output voltages based a single operational amplifier output voltage generated with the single operational amplifier and feedback loop.