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Patent Agency Ranking
公开(公告)号：US20190195948A1
公开(公告)日：2019-06-27
申请号：US15852407
申请日：2017-12-22
Applicant: SanDisk Technologies LLC
Inventor： Amandeep Kaur , Sridhar Yadala , Jayanth Mysore Thimmaiah , Ravindra Arjun Madpur
IPC: G01R31/319 , G05B17/02 , G06F17/50 , G05B23/02 , G11C11/4072 , G11C29/02 , G11C29/50 , G11C7/20
Abstract: Disclosed is an apparatus including a datapath and a test circuit. The datapath is configured to transfer data between a memory core and an IO interface. The datapath includes a plurality of circuits, and a memory core interface. The plurality of circuits operates according to a supply voltage. The test circuit is coupled to the datapath, and configured to determine, from a set of operable voltage levels of the supply voltage, a first minimum operable voltage level for the datapath to operate for the data traversing the datapath at a first frequency.
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公开(公告)号：US10725104B2
公开(公告)日：2020-07-28
申请号：US15852407
申请日：2017-12-22
Applicant: SanDisk Technologies LLC
Inventor： Amandeep Kaur , Sridhar Yadala , Jayanth Mysore Thimmaiah , Ravindra Arjun Madpur
IPC: G01R31/28 , G01R31/319 , G05B17/02 , G05B23/02 , G11C29/02 , G11C11/4072 , G01R31/30 , G06F30/327 , G11C29/50 , G11C7/20 , G11C5/14
Abstract: Disclosed is an apparatus including a datapath and a test circuit. The datapath is configured to transfer data between a memory core and an IO interface. The datapath includes a plurality of circuits, and a memory core interface. The plurality of circuits operates according to a supply voltage. The test circuit is coupled to the datapath, and configured to determine, from a set of operable voltage levels of the supply voltage, a first minimum operable voltage level for the datapath to operate for the data traversing the datapath at a first frequency.
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公开(公告)号：US10001797B2
公开(公告)日：2018-06-19
申请号：US15218566
申请日：2016-07-25
Applicant: SanDisk Technologies LLC
Inventor： Srinivasa Rao Sabbineni , Bhavin Odedara , Jayanth Mysore Thimmaiah
Abstract: Regulator circuitry may include a plurality of output circuits to generate a plurality of regulated output voltages. The regulator circuitry may include a single operational amplifier and a single feedback loop for regulation, which may reduce space and power consumed by the regulator circuitry. A transconductor and current mirror circuitry may be included to generate the plurality of regulated output voltages based a single operational amplifier output voltage generated with the single operational amplifier and feedback loop.
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公开(公告)号：US20180026646A1
公开(公告)日：2018-01-25
申请号：US15218638
申请日：2016-07-25
Applicant: SanDisk Technologies LLC
Inventor： Bhavin Odedara , Srikanth Bojja , Jayanth Mysore Thimmaiah , Srinivasa Rao Sabbineni
CPC classification number: H03L7/099 , H03B27/00 , H03L7/0891 , H03L7/093 , H03L7/0995 , H03L7/0997 , H03L2207/06
Abstract: A phase-locked loop (PLL) circuit may be configured to generate a plurality of oscillating signals based on a single control voltage generated based on a phase difference between an input signal and a feedback signal. One of the plurality of oscillating signals may be used to generate the feedback signal.
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公开(公告)号：US20180024581A1
公开(公告)日：2018-01-25
申请号：US15218566
申请日：2016-07-25
Applicant: SanDisk Technologies LLC
Inventor： Srinivasa Rao Sabbineni , Bhavin Odedara , Jayanth Mysore Thimmaiah
Abstract: Regulator circuitry may include a plurality of output circuits to generate a plurality of regulated output voltages. The regulator circuitry may include a single operational amplifier and a single feedback loop for regulation, which may reduce space and power consumed by the regulator circuitry. A transconductor and current mirror circuitry may be included to generate the plurality of regulated output voltages based a single operational amplifier output voltage generated with the single operational amplifier and feedback loop.
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