公开(公告)号：US12105490B2

公开(公告)日：2024-10-01

申请号：US17492908

申请日：2021-10-04

Applicant: Schweitzer Engineering Laboratories, Inc.

Inventor： Sreenivas Dingari ,  Angelo D'Aversa ,  Veselin Skendzic ,  Chandrasekaran Swaminathan ,  Greg Rzepka

IPC: G05B19/042 ,  G06F3/06 ,  H02H1/00

CPC classification number: G05B19/042 ,  G06F3/0604 ,  G06F3/0646 ,  G06F3/0673 ,  G05B2219/24215 ,  G05B2219/2639 ,  H02H1/0092

Abstract: Systems, devices, and methods include protection functions in an electrical power system. A processing subsystem may include a processor. A memory subsystem may comprise a first memory section and a second memory section. A memory management subsystem may, in a first operational mode, enable memory access between the processor and the first memory section and the second memory section and, in a second operational mode, enable memory access between the processor and only the first memory section.

公开(公告)号：US20230018371A1

公开(公告)日：2023-01-19

申请号：US17372887

申请日：2021-07-12

Applicant: Schweitzer Engineering Laboratories, Inc.

Inventor： Manodev J. Rajasekaran ,  Greg Rzepka

IPC: H04L12/741 ,  H04L12/761 ,  H04L12/947 ,  H04L12/935

Abstract: A method includes obtaining, via a power system device, a source media access control (SMAC) address. The method includes generating, via the power system device, an Ethernet frame of power system data with a destination media access control (DMAC) address comprising at least a portion of the SMAC address. The method includes sending, via the power system device, the Ethernet frame to an intelligent electronic device (IED) of a power system.

公开(公告)号：US11736569B2

公开(公告)日：2023-08-22

申请号：US17456190

申请日：2021-11-23

Applicant: Schweitzer Engineering Laboratories, Inc

Inventor： Sreenivas Dingari ,  Veselin Skendzic ,  Hamza Abubakari ,  Greg Rzepka ,  Angelo D'Aversa ,  Balaji Janarthanan ,  Chandrasekaran Swaminathan ,  Jyotsna Samhita Gokavarapu

IPC: G06F15/16 ,  H04L67/12 ,  H02J13/00

CPC classification number: H04L67/12 ,  H02J13/0004 ,  H02J13/00028

Abstract: The present disclosure relates to systems and methods for processing a stream of messages in an electric power system (EPS). In one embodiment, a system may include a configuration subsystem to receive a plurality of criteria from an operator to identify a subset of the stream of messages for real-time processing. A receiver subsystem may identify the subset of the stream of messages based on at least one criterion from the plurality of criteria. A real-time processing subsystem may receive the subset of the stream of messages from the receiver subsystem, process the stream of messages within a fixed interval of a time of receipt, and update a value based on information in the processed stream of messages. A protective action subsystem may implement a protective action based on information in the processed stream of messages.

公开(公告)号：US11552891B1

公开(公告)日：2023-01-10

申请号：US17372887

申请日：2021-07-12

Applicant: Schweitzer Engineering Laboratories, Inc.

Inventor： Manodev J. Rajasekaran ,  Greg Rzepka

IPC: H04L45/745 ,  H04L49/00 ,  H04L49/25 ,  H04L45/16

Abstract: A method includes obtaining, via a power system device, a source media access control (SMAC) address. The method includes generating, via the power system device, an Ethernet frame of power system data with a destination media access control (DMAC) address comprising at least a portion of the SMAC address. The method includes sending, via the power system device, the Ethernet frame to an intelligent electronic device (IED) of a power system.

公开(公告)号：US11128481B2

公开(公告)日：2021-09-21

申请号：US16414449

申请日：2019-05-16

Applicant: Schweitzer Engineering Laboratories, Inc.

Inventor： Manodev J. Rajasekaran ,  Greg Rzepka ,  Bryon S. Bridges

IPC: H04L12/10

Abstract: Disclosed herein are systems for hardware accelerated communications between devices for the protection of electric power delivery systems. For example, a merging unit may include input circuitry that receives a monitoring signal indicating an electrical characteristic of a power line. The merging unit may include pre-payload circuitry that generates at least portions of preset metadata of a communication frame. The merging unit may include payload generation circuitry that generates payload data of the communication frame based at least in part on the electrical characteristic. The merging unit may include a communication interface that sends the communication frame to a receiving device.

公开(公告)号：US11934169B2

公开(公告)日：2024-03-19

申请号：US17308152

申请日：2021-05-05

Applicant: Schweitzer Engineering Laboratories, Inc.

Inventor： Brian James Peterson ,  Evan J. Penberthy ,  Greg Rzepka

IPC: G05B19/042 ,  H02H1/00 ,  H01H47/00

CPC classification number: G05B19/0425 ,  H02H1/0092 ,  G05B2219/1157 ,  G05B2219/1182 ,  G05B2219/21117 ,  G05B2219/21127 ,  G05B2219/21157 ,  G05B2219/21159 ,  H01H47/007 ,  H02H1/0061

Abstract: Configurable binary circuits for use in electrical power systems may include an input/output port, a binary input subsystem for receiving a binary input signal, a binary output subsystem for transmitting a binary output signal, and a switch subsystem for selecting one of the binary input subsystem or the binary output subsystem for operation. Intelligent electronic devices (IEDs) and associated methods may include one or more configurable binary circuits.

公开(公告)号：US11862958B2

公开(公告)日：2024-01-02

申请号：US17492898

申请日：2021-10-04

Applicant: Schweitzer Engineering Laboratories, Inc.

Inventor： Sreenivas Dingari ,  Angelo D'Aversa ,  Veselin Skendzic ,  Greg Rzepka

IPC: G05B19/042 ,  H02H1/00 ,  H02J13/00 ,  H02H7/26

CPC classification number: H02H1/0092 ,  G05B19/0428 ,  H02H7/26 ,  H02J13/00001 ,  G05B2219/21154 ,  G05B2219/21169

Abstract: Systems, devices, and methods include protection functions in an electrical power system. For example, a processing subsystem may include a processor. A memory subsystem may comprise a first memory section and a second memory section. A memory management subsystem may enable memory access only between the processor and only the first memory section to initialize the at least one protection function and, after initialization of the at least one protection function, enable memory access between the processor and the second memory section. Such a configuration may enable the protection functions as fast as possible without waiting for the functions of lesser criticality to be fully loaded and become operational.

公开(公告)号：US20230164220A1

公开(公告)日：2023-05-25

申请号：US17456190

申请日：2021-11-23

Applicant: Schweitzer Engineering Laboratories, Inc

Inventor： Sreenivas Dingari ,  Veselin Skendzic ,  Hamza Abubakari ,  Greg Rzepka ,  Angelo D'Aversa ,  Balaji Janarthanan ,  Chandrasekaran Swaminathan ,  Jyotsna Samhita Gokavarapu

IPC: H04L67/12 ,  H02J13/00

CPC classification number: H04L67/12 ,  H02J13/0004 ,  H02J13/00028

Abstract: The present disclosure relates to systems and methods for processing a stream of messages in an electric power system (EPS). In one embodiment, a system may include a configuration subsystem to receive a plurality of criteria from an operator to identify a subset of the stream of messages for real-time processing. A receiver subsystem may identify the subset of the stream of messages based on at least one criterion from the plurality of criteria. A real-time processing subsystem may receive the subset of the stream of messages from the receiver subsystem, process the stream of messages within a fixed interval of a time of receipt, and update a value based on information in the processed stream of messages. A protective action subsystem may implement a protective action based on information in the processed stream of messages.

公开(公告)号：US20220359142A1

公开(公告)日：2022-11-10

申请号：US17308152

申请日：2021-05-05

Applicant: Schweitzer Engineering Laboratories, Inc.

Inventor： Brian James Peterson ,  Evan J. Penberthy ,  Greg Rzepka

IPC: H01H47/00 ,  H02H1/00

Abstract: Configurable binary circuits for use in electrical power systems may include an input/output port, a binary input subsystem for receiving a binary input signal, a binary output subsystem for transmitting a binary output signal, and a switch subsystem for selecting one of the binary input subsystem or the binary output subsystem for operation. Intelligent electronic devices (IEDs) and associated methods may include one or more configurable binary circuits.

公开(公告)号：US10979330B2

公开(公告)日：2021-04-13

申请号：US16414471

申请日：2019-05-16

Applicant: Schweitzer Engineering Laboratories, Inc.

Inventor： Manodev J. Rajasekaran ,  Greg Rzepka ,  Bryon S. Bridges

IPC: H04L12/26 ,  H02H3/10 ,  H02H1/00 ,  G01R31/08

Abstract: Disclosed herein is a system for time aligning electric power system measurements at an intelligent electronic device (IED) from signals from merging units where the merging unit does not require a common or external time source. Communications from merging units may arrive at different times due to differences in communication latency or other factor. The IED may associate digital samples from merging units with a local time domain of the IED based on the data acquisition, data processing, and data communication latency in communicating with the merging units.