公开(公告)号：US10706886B1

公开(公告)日：2020-07-07

申请号：US16369380

申请日：2019-03-29

Applicant: Seagate Technology LLC

Inventor： Vidur Fnu Parkash ,  Mark Allen Gaertner

IPC: G11B5/54 ,  G11B21/10 ,  G11B5/012 ,  G11B5/55 ,  G11B5/48 ,  G06F3/06 ,  G11B27/36

Abstract: A first time period is determined during which a first head driven by a first actuator will be performing a track-following operation. A second time period is also determined during which a second head driven by a second actuator will be performing a low-priority disk access operation that includes a seek. The first and second actuators are independently movable such that the first and second disk access operations are capable of being performed in parallel. If it is determined that the seek of the second head will impact servo control of the track-following operation of the first head, a start time of the seek of the second head is changed to correspond to a time that mitigates impacts to the track-following operation of the first head.

公开(公告)号：US10249339B1

公开(公告)日：2019-04-02

申请号：US16020501

申请日：2018-06-27

Applicant: Seagate Technology LLC

Inventor： Riyan Mendonsa ,  Jason Bryce Gadbois ,  Mark Allen Gaertner ,  Guy T. Lawrence ,  Bruce Douglas Buch

IPC: G11B27/36 ,  G11B21/08 ,  G11B5/012

Abstract: One or more magnetic recording disks are coupled to a spindle motor, each of the disks having opposing recording surfaces. Two or more actuators are moveable independently over at least a first recording surface of the one or more disks. A first actuator of the two or more actuators comprises a first write head and a first read head. A second actuator of the two or more actuators comprises at least a second read head and may include a second write head. A controller is coupled to the two or more actuators and configured to write data to a track on the first recording surface using the first write head, and perform a read operation on the data written to the track using the second read head. The controller is also configured to verify that the data was successfully written to the track in response to the read operation. The read operation can be performed within less than one revolution of the first recording surface after the write operation.

公开(公告)号：US20170206161A1

公开(公告)日：2017-07-20

申请号：US15477353

申请日：2017-04-03

Applicant: Seagate Technology LLC

Inventor： Timothy R. Feldman ,  Andrew M. Kowles ,  Mark Allen Gaertner ,  Brian T. Edgar

IPC: G06F12/0811 ,  G06F12/06

CPC classification number: G06F12/0811 ,  G06F12/0246 ,  G06F12/06 ,  G06F2212/1016 ,  G06F2212/283 ,  G06F2212/608 ,  G11B20/10527 ,  G11B20/1252 ,  G11C7/1012 ,  G11C2207/2245

Abstract: A data storage device includes one or more storage media that include multiple physical storage locations. The device also includes at least one cache memory having a logical space that includes a plurality of separately managed logical block address (LBA) ranges. Additionally, a controller is included in the device. The controller is configured to receive data extents addressed by a first LBA and a logical block count. The controller is also configured to identify at least one separately managed LBA range of the plurality of separately managed LBA ranges in the at least one cache memory based on LBAs associated with at least some of the received data extents. The controller stores the at least some of the received data extents in substantially monotonically increasing LBA order in at least one physical storage location, of the at least one cache memory, assigned to the identified at least one LBA range.

公开(公告)号：US09448896B2

公开(公告)日：2016-09-20

申请号：US13961755

申请日：2013-08-07

Applicant: Seagate Technology LLC

Inventor： Mark Allen Gaertner ,  Jon Trantham ,  Vidya Krishnamurthy ,  Steve Faulhaber ,  Yong Yang

IPC: G06F11/00 ,  G06F11/16 ,  G06F11/14 ,  G06F11/20

CPC classification number: G06F11/1666 ,  G06F11/1441 ,  G06F11/2015

Abstract: Torn write mitigation circuitry determines if a write operation to memory is in progress at or about a time of power loss. In response to the write operation being in progress at or about the time of the power loss, the torn write mitigation circuitry causes torn write data and metadata to be stored to a non-volatile cache. The torn write data comprise data left in a degraded or uncorrectable state as a result of the loss of power. The metadata describe the torn write data.

Abstract translation: 被破坏的写入缓冲电路确定在功率损耗时间或约一个时间内对存储器的写入操作是否正在进行。 为了响应于在功率损耗的时间或周围的写入操作，被破坏的写入缓冲电路导致撕裂的写入数据和元数据被存储到非易失性高速缓存。 被破坏的写数据包括由于功率损失而处于劣化或不可校正状态的数据。 元数据描述了被破坏的写入数据。

公开(公告)号：US20160154738A1

公开(公告)日：2016-06-02

申请号：US14558396

申请日：2014-12-02

Applicant: Seagate Technology LLC

Inventor： Mark Allen Gaertner ,  Mehmet Fatih Erden

IPC: G06F12/08

CPC classification number: G06F12/0871 ,  G06F3/0605 ,  G06F3/064 ,  G06F3/0676 ,  G06F2212/211 ,  G06F2212/224 ,  G06F2212/7201 ,  G11B20/1217 ,  G11B27/00 ,  G11B27/3027 ,  G11B2020/1267

Abstract: A storage media comprising a first storage subset with a first value of a storage media characteristic and a second storage subset with a second value of the storage media characteristic, the first value of a storage media characteristic being substantially different than the second value of the storage media characteristic and a storage controller configured to allocate a plurality of logical block addresses (LBAs) between the first storage subset and the second storage subset based on a predetermined criterion in view of the first value of the storage media characteristic and the second value of the storage media characteristic.

Abstract translation: 一种存储介质，包括具有存储介质特性的第一值的第一存储子集和具有所述存储介质特性的第二值的第二存储子集，所述存储介质特性的第一值基本上不同于所述存储器的第二值 媒体特性和存储控制器，其被配置为基于预定标准在第一存储子集和第二存储子集之间分配多个逻辑块地址（LBA），根据存储介质特性的第一值和 存储介质特性。

公开(公告)号：US09164837B2

公开(公告)日：2015-10-20

申请号：US14025277

申请日：2013-09-12

Applicant: Seagate Technology LLC

Inventor： Mark Allen Gaertner ,  Bruce Douglas Buch ,  Ryan James Goss

IPC: G06F11/10 ,  G06F12/02

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7207

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a non-volatile memory is arranged into a plurality of blocks, with each of the blocks constituting an integral plural number N of fixed-sized, multi-bit transfer units. A processing circuit retrieves at least a portion of the data stored in a selected block to a volatile memory buffer in response to a transfer unit (TU) bit map. The TU bit map is stored in a memory and provides a multi-bit sequence of bits corresponding to the N transfer units of the selected block. The values of the bits in the multi-bit sequence of bits indicate whether the corresponding transfer units are to be retrieved.

Abstract translation: 用于管理诸如闪存之类的存储器中的数据的方法和装置。 根据一些实施例，非易失性存储器被布置成多个块，其中每个块构成固定大小的多位传输单元的整数个数量N。 处理电路响应于传送单元（TU）位图，将存储在所选块中的数据的至少一部分检索到易失性存储器缓冲器。 TU位图被存储在存储器中并且提供与所选块的N个传送单元相对应的位的多位序列。 多比特序列中的比特值表示是否检索相应的传送单元。

公开(公告)号：US09043668B2

公开(公告)日：2015-05-26

申请号：US13762436

申请日：2013-02-08

Applicant: Seagate Technology LLC

Inventor： Ryan James Goss ,  Mark Allen Gaertner ,  Jon D. Trantham

IPC: H03M13/00 ,  H03M13/29

CPC classification number: H03M13/2906 ,  G06F11/1048

Abstract: Method and apparatus for managing data in a memory. In accordance with some embodiments, a first data object and an associated first ECC data set are generated and stored in a non-volatile (NV) main memory responsive to a first set of data blocks having a selected logical address. A second data object and an associated second ECC data set are generated responsive to receipt of a second set of data blocks having the selected logical address. The second data object and the second ECC data set are subsequently stored in the in the NV main memory responsive to a mismatch between the first ECC data set and the second ECC data set.

Abstract translation: 用于管理存储器中的数据的方法和装置。 根据一些实施例，响应于具有所选逻辑地址的第一组数据块，生成第一数据对象和相关联的第一ECC数据集并将其存储在非易失性（NV）主存储器中。 响应于接收到具有所选逻辑地址的第二组数据块，产生第二数据对象和相关联的第二ECC数据集。 随后，第二数据对象和第二ECC数据集随后存储在NV主存储器中，以响应第一ECC数据集和第二ECC数据集之间的不匹配。

公开(公告)号：US20150143039A1

公开(公告)日：2015-05-21

申请号：US14599725

申请日：2015-01-19

Applicant: Seagate Technology LLC

Inventor： Ryan James Goss ,  David Scott Seekins ,  Mark Allen Gaertner

IPC: G06F12/02

CPC classification number: G06F12/0261 ,  G06F12/0246 ,  G06F2212/702 ,  G06F2212/7205

Abstract: Method and apparatus for managing a memory, such as but not limited to a flash memory. In accordance with some embodiments, initial state information is stored which identifies an actual state of a garbage collection unit (GCU) of a memory during a normal operational mode. During a restoration mode after a memory power cycle event, a virtualized state of the GCU is determined responsive to the initial state information and to data read from the GCU. The memory is transitioned from the restoration mode to the normal operational mode once the virtualized state for the GCU is determined.

Abstract translation: 用于管理存储器的方法和装置，例如但不限于闪速存储器。 根据一些实施例，存储在正常操作模式期间识别存储器的垃圾回收单元（GCU）的实际状态的初始状态信息。 在存储器电源循环事件之后的恢复模式期间，响应于初始状态信息和从GCU读取的数据确定GCU的虚拟化状态。 一旦确定了GCU的虚拟化状态，存储器将从恢复模式转换到正常操作模式。

公开(公告)号：US20150089278A1

公开(公告)日：2015-03-26

申请号：US14034251

申请日：2013-09-23

Applicant: Seagate Technology LLC

Inventor： Ara Patapoutian ,  Bruce Douglas Buch ,  Ryan James Goss ,  Mark Allen Gaertner ,  Arvind Sridharan

IPC: G06F11/10

CPC classification number: G06F11/1048

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory has a plurality of solid-state non-volatile memory cells. A processing circuit is connected to the memory and configured to direct the execution of a plurality of read error recovery routines in response to at least one uncorrectable read error in a data set retrieved from the memory. The recovery routines are executed in a selected order based on an elapsed recovery time parameter for each of the recovery routines and an estimated probability of success of each of the recovery routines.

Abstract translation: 用于管理诸如闪存之类的存储器中的数据的方法和装置。 根据一些实施例，存储器具有多个固态非易失性存储单元。 处理电路连接到存储器并且被配置为响应于从存储器检索的数据集中的至少一个不可校正的读取错误来引导执行多个读取错误恢复例程。 基于每个恢复例程的经过恢复时间参数和每个恢复例程的估计的成功概率，以所选择的顺序执行恢复例程。

公开(公告)号：US20150074487A1

公开(公告)日：2015-03-12

申请号：US14025327

申请日：2013-09-12

Applicant: Seagate Technology LLC

Inventor： Ara Patapoutian ,  Ryan James Goss ,  Mark Allen Gaertner ,  Bruce Douglas Buch ,  Arvind Sridharan

IPC: G06F11/10

CPC classification number: G06F11/1012

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, the apparatus has a solid-state non-volatile memory and a processing circuit configured to write data to a selected location of the memory. The data are arranged in the form of multi-bit code words each comprising a user data payload and associated parity data configured to correct one or more bit errors in the user data payload. The processing circuit adjusts at least a selected one of a size of the code words, a size of the user data payloads or a size of the parity data responsive to at least a selected one of an accumulated count of access operations upon the selected location or an error rate associated with the selected location.

Abstract translation: 用于管理诸如闪存之类的存储器中的数据的方法和装置。 根据一些实施例，该装置具有固态非易失性存储器和被配置为将数据写入存储器的选定位置的处理电路。 数据以多位码字的形式排列，每个码字包括用户数据有效载荷和被配置为校正用户数据有效载荷中的一个或多个位错误的相关联的奇偶校验数据。 所述处理电路至少根据所选择的位置的访问操作的累积计数中的至少一个来选择所述码字的大小，所述用户数据有效载荷的大小或所述奇偶校验数据的大小中的一个， 与所选位置相关联的错误率。