公开(公告)号：US10909051B2

公开(公告)日：2021-02-02

申请号：US15610815

申请日：2017-06-01

Applicant: Seagate Technology LLC

Inventor： Timothy Canepa

IPC: G06F13/16 ,  G06F13/40 ,  G11C16/10 ,  G11C16/26

Abstract: Method and apparatus for managing a non-volatile memory (NVM). In some embodiments, a memory module has a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A controller is adapted to communicate commands and data to the MME circuit via an intervening data bus. The controller operates to reset the MME circuit by issuing a reset command to the MME circuit over the data bus, activating a decoupling circuit coupled between the data bus and a reference line at a reference voltage level to remove capacitance from the data bus resulting from the reset command, and subsequently sensing a voltage on the data bus. In some cases, multiple MME circuits and NVMs may be arranged on a plurality of flash dies which are concurrently reset by the controller.

公开(公告)号：US10664168B2

公开(公告)日：2020-05-26

申请号：US16201767

申请日：2018-11-27

Applicant: Seagate Technology LLC

Inventor： Timothy Canepa ,  Stephen Hanna

IPC: G06F12/02 ,  G06F3/06 ,  G06F13/16

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit. A controller circuit communicates a first command to the MME circuit to perform a selected action upon a selected address of the NVM. After a variable delay time interval, a second command is communicated by the controller circuit to the MME circuit as a status request regarding the first command. The variable delay time interval is determined based on an accumulated count of status requests that were issued, prior to the first command, for the selected address.

公开(公告)号：US20190058583A1

公开(公告)日：2019-02-21

申请号：US16165582

申请日：2018-10-19

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Timothy Canepa ,  Ramdas Kachare

IPC: H04L9/08 ,  H04L9/32

CPC classification number: H04L9/088 ,  G06F12/1408 ,  G06F2212/1052 ,  H04L9/0838 ,  H04L9/0897 ,  H04L9/3228

Abstract: Systems and methods for using encryption keys to manage data retention are described. In one embodiment, the systems and methods may include receiving data such as user data from a host of the storage drive, encrypting the data using an encryption key, writing the encrypted data to the storage drive, and retaining the encrypted data on the storage drive based at least in part on a validity of the encryption key.

公开(公告)号：US20180341403A1

公开(公告)日：2018-11-29

申请号：US15606549

申请日：2017-05-26

Applicant: Seagate Technology LLC

Inventor： Timothy Canepa ,  Stephen Hanna

IPC: G06F3/06

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit. A controller circuit communicates a first command to the MME circuit to perform a selected action upon a selected address of the NVM. After a variable delay time interval, a second command is communicated by the controller circuit to the MME circuit as a status request regarding the first command. The variable delay time interval is determined based on an accumulated count of status requests that were issued, prior to the first command, for the selected address.

公开(公告)号：US10140215B1

公开(公告)日：2018-11-27

申请号：US15606502

申请日：2017-05-26

Applicant: Seagate Technology LLC

Inventor： Timothy Canepa ,  Jeffrey Munsil ,  Jackson Ellis ,  Mark Ish

IPC: G06F12/00 ,  G06F12/1009 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F12/1009 ,  G06F3/0613 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1024 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/7201

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A map structure associates logical addresses of user data blocks with physical addresses in the NVM at which the user data blocks are stored. A controller circuit arranges the user data blocks into map units (MUs), and directs the MME circuit to write the MUs to a selected page of the NVM. The controller circuit updates the map structure to list only a single occurrence of a physical address for all of the MUs written to the selected page. The map structure is further updated to list an MU offset and an MU length for each of the MUs written to the selected page.

公开(公告)号：US20180210832A1

公开(公告)日：2018-07-26

申请号：US15411679

申请日：2017-01-20

Applicant: Seagate Technology LLC

Inventor： Alex Tang ,  Leonid Baryudin ,  Timothy Canepa ,  Jackson Ellis

IPC: G06F12/0808 ,  G06F3/06 ,  G06F12/128

Abstract: The implementations described herein provide a hybrid drive with a storage capacity including solid-state drive (NAND) technology and hard disc drive (HDD) technology. A translation layer is stored in the solid-state drive and includes plurality of entries. Each entry of the plurality of entries corresponds to at least one logical data unit and includes a cache state indicating where the data corresponding to the logical data unit is located and whether the data is valid. The translation layer may be a multi-layer map that includes a sparse mapping scheme. In a sparse multi-layer map, entries are leaf entries or non-leaf entries. Leaf entries include a cache state for the corresponding logical data unit(s). Non-leaf entries may include a pointer to a lower level mapping for a plurality of logical data units.

公开(公告)号：US20180210675A1

公开(公告)日：2018-07-26

申请号：US15411550

申请日：2017-01-20

Applicant: Seagate Technology LLC

Inventor： Alex Tang ,  Leonid Baryudin ,  Timothy Canepa ,  Mark Ish ,  Jackson Ellis

IPC: G06F3/06

CPC classification number: G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7205

Abstract: A garbage collection method comprises selecting one or blocks in a SSD of a hybrid drive for garbage collection; determining a state of data of the one or more selected blocks, wherein the state suggests a location and temperature of data; and executing a garbage collection efficiency and caching efficiency action on the data of the one or more selected blocks based on the determined state. The garbage collection process may utilize the state information provided by the cache layer of the hybrid drive to make decisions regarding data in the one or more selected blocks.

公开(公告)号：US10740251B2

公开(公告)日：2020-08-11

申请号：US15411679

申请日：2017-01-20

Applicant: Seagate Technology LLC

Inventor： Alex Tang ,  Leonid Baryudin ,  Timothy Canepa ,  Jackson Ellis

IPC: G06F12/128 ,  G06F12/02 ,  G06F12/0868 ,  G06F12/0888

Abstract: The implementations described herein provide a hybrid drive with a storage capacity including solid-state drive (NAND) technology and hard disc drive (HDD) technology. A translation layer is stored in the solid-state drive and includes plurality of entries. Each entry of the plurality of entries corresponds to at least one logical data unit and includes a cache state indicating where the data corresponding to the logical data unit is located and whether the data is valid. The translation layer may be a multi-layer map that includes a sparse mapping scheme. In a sparse multi-layer map, entries are leaf entries or non-leaf entries. Leaf entries include a cache state for the corresponding logical data unit(s). Non-leaf entries may include a pointer to a lower level mapping for a plurality of logical data units.

公开(公告)号：US20180349148A1

公开(公告)日：2018-12-06

申请号：US15608127

申请日：2017-05-30

Applicant: Seagate Technology LLC

Inventor： Mark Ish ,  Timothy Canepa ,  David S. Ebsen

IPC: G06F9/44 ,  G06F12/0888

Abstract: A data storage device may consist of a non-volatile memory having rewritable in-place memory cells each with a read-write asymmetry. The non-volatile memory can store boot data that is subsequently loaded by a selection module of the data storage device. The selection module may bypass a memory buffer of the data storage device to load the boot data.

公开(公告)号：US20180349035A1

公开(公告)日：2018-12-06

申请号：US15608203

申请日：2017-05-30

Applicant: Seagate Technology LLC

Inventor： Jackson Ellis ,  Jeffrey Munsil ,  Timothy Canepa ,  Stephen Hanna

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

Abstract: A data storage device with one or more buffers can employ buffer tenure management with at least a data storage device having a first buffer, a second buffer, a buffer manager, and a non-volatile memory. The first buffer can be located on-chip while the second buffer is located off-chip. The first buffer may be filled with data having a tenure of less than a predetermined tenure threshold as directed by the buffer manager.