公开(公告)号：US08214172B2

公开(公告)日：2012-07-03

申请号：US12393533

申请日：2009-02-26

Applicant: Seongmoon Wang ,  Xiangyu Tang

Inventor： Seongmoon Wang ,  Xiangyu Tang

IPC: G01R31/00

CPC classification number: G01R31/318547

Abstract: According to exemplary methods and systems of the present principles, the location of defective field repairable units (FRUS) of a circuit that have varying sizes or varying numbers of scan cells may be identified by employing tiles including scan cells from different FRUS. A set of test patterns may be scanned through the scan cells such that cells belonging to FRUs within a tile may be concealed while analyzing the response of scan cells in the tile contributed by a different FRU. Further, defective tiles are discoverable at any tile location and in any quantity within a maximal capacity using a compressed signature. In addition, signature registers that process data at a rate that is faster than the scan shift rate of the circuit may be employed during compression to multiply a circuit response by a plurality of components of a compression matrix during one scan shift cycle.

Abstract translation: 根据本原理的示例性方法和系统，可以通过使用包括来自不同FRUS的扫描单元的瓦片来识别具有不同大小或不同数目的扫描单元的电路的缺陷现场修复单元（FRUS）的位置。 可以通过扫描单元扫描一组测试图案，使得属于瓦片内的FRU的单元可以被隐藏，同时分析由不同FRU贡献的瓦片中的扫描单元的响应。 此外，在任何瓦片位置和使用压缩签名的最大容量内的任何数量中都可以发现有缺陷的瓦片。 此外，在压缩期间可以采用以比电路的扫描偏移速率更快的速率处理数据的签名寄存器，以在一个扫描移位周期期间乘以压缩矩阵的多个分量的电路响应。

公开(公告)号：US07610527B2

公开(公告)日：2009-10-27

申请号：US11276771

申请日：2006-03-14

Applicant: Seongmoon Wang ,  Kedarnath J Balakrishnan ,  Srimat T Chakradhar

Inventor： Seongmoon Wang ,  Kedarnath J Balakrishnan ,  Srimat T Chakradhar

IPC: G06F11/00 ,  G01R31/28

CPC classification number: G01R31/318335 ,  G01R31/3181

Abstract: Implementations of the present principles are directed to test output compaction arrangements and a methods of generating control patterns for unknown blocking. The specified bits in the control patterns, which when using linear feedback shift register (LFSR) reseeding determines control data volume and LFSR size, are preferably organized in a manner so as to balance the number of specified bits in the control patterns across test patterns.

Abstract translation: 本原理的实现涉及测试输出压缩布置以及产生未知阻塞的控制模式的方法。 当使用线性反馈移位寄存器（LFSR）重新进给确定控制数据量和LFSR大小时，控制模式中的指定位优选地以使得跨越测试模式平衡控制模式中的指定位的数目的方式来组织。

公开(公告)号：US07484151B2

公开(公告)日：2009-01-27

申请号：US11538245

申请日：2006-10-03

Applicant: Kedarnath Balakrishnan ,  Seongmoon Wang ,  Wenlong Wei ,  Srimat T. Chakradhar

Inventor： Kedarnath Balakrishnan ,  Seongmoon Wang ,  Wenlong Wei ,  Srimat T. Chakradhar

IPC: G01R31/28

CPC classification number: G01R31/31921

Abstract: Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor is configured to generate a test pattern from the seed and the locations of scan inputs. The decompressor includes a first test pattern generator, a second test pattern generator, and a selector configured to select the test pattern generated by the first test pattern generator or the test pattern generated by the second test pattern generator using the locations of scan inputs.

Abstract translation: 公开了一种包括解压缩器和与解压缩器通信的测试器的逻辑测试系统。 测试器被配置为存储种子和扫描输入的位置，并且还被配置为将种子和扫描输入的位置传送到解压缩器。 解压缩器被配置为从种子和扫描输入的位置生成测试图案。 解压缩器包括第一测试图案发生器，第二测试图案发生器和被配置为选择由第一测试图案发生器生成的测试图案或由第二测试图案发生器使用扫描输入位置产生的测试图案的选择器。

公开(公告)号：US20080091998A1

公开(公告)日：2008-04-17

申请号：US11851137

申请日：2007-09-06

Applicant: Seongmoon Wang

Inventor： Seongmoon Wang

IPC: G01R31/3183

CPC classification number: G01R31/318547 ,  G01R31/318328

Abstract: A method includes selecting at least one regular scan cell that is replaced with a corresponding one of an enhanced scan cell in a scan chain for scan based delay testing of the digital circuit, controlling the enhanced scan cell with a skewed load approach, and controlling regular scan cells of the scan chain with a broadside approach. More specifically, this reduces test sequence lengths and achieves higher delay fault coverage, without having to pay high cost to drive all scan cells by the skewed load approach, which requires a faster switching than the broadside approach. No additional pins are required for driving enhanced scan cells because the drive signal for switching the enhanced scan cells is derived from the signal for driving the regular scan cells.

Abstract translation: 一种方法包括选择至少一个常规扫描单元，其被扫描链中的增强扫描单元中的对应的一个扫描单元替换，用于数字电路的基于扫描的延迟测试，以偏斜负载方式控制增强型扫描单元， 扫描链的扫描细胞具有宽边方法。 更具体地说，这降低了测试序列长度并且实现了更高的延迟故障覆盖，而不需要通过偏斜负载方法支付高的驱动所有扫描单元的成本，这需要比宽边方法更快的切换。 由于用于切换增强扫描单元的驱动信号是从用于驱动常规扫描单元的信号导出的，所以驱动增强型扫描单元不需要额外的引脚。

公开(公告)号：US07284176B2

公开(公告)日：2007-10-16

申请号：US10891618

申请日：2004-07-15

Applicant: Seongmoon Wang ,  Srimat T. Chakradhar

Inventor： Seongmoon Wang ,  Srimat T. Chakradhar

IPC: G01R31/28 ,  G06F17/50

CPC classification number: G01R31/318335 ,  G01R31/318385 ,  G01R31/31921

Abstract: The present invention is directed to a logic testing architecture with an improved decompression engine and a method of decompressing scan chains for testing logic circuits.

Abstract translation: 本发明涉及具有改进的解压缩引擎的逻辑测试架构和用于测试逻辑电路的解压缩扫描链的方法。

公开(公告)号：US20070113129A1

公开(公告)日：2007-05-17

申请号：US11538245

申请日：2006-10-03

Applicant: Kedarnath Balakrishnan ,  Seongmoon Wang ,  Wenlong Wei ,  Srimat Chakradhar

Inventor： Kedarnath Balakrishnan ,  Seongmoon Wang ,  Wenlong Wei ,  Srimat Chakradhar

IPC: G01R31/28 ,  G06F11/00

CPC classification number: G01R31/31921

Abstract: Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor is configured to generate a test pattern from the seed and the locations of scan inputs. The decompressor includes a first test pattern generator, a second test pattern generator, and a selector configured to select the test pattern generated by the first test pattern generator or the test pattern generated by the second test pattern generator using the locations of scan inputs.

Abstract translation: 公开了一种包括解压缩器和与解压缩器通信的测试器的逻辑测试系统。 测试器被配置为存储种子和扫描输入的位置，并且还被配置为将种子和扫描输入的位置传送到解压缩器。 解压缩器被配置为从种子和扫描输入的位置生成测试图案。 解压缩器包括第一测试图案发生器，第二测试图案发生器和被配置为选择由第一测试图案发生器生成的测试图案或由第二测试图案发生器使用扫描输入位置产生的测试图案的选择器。

公开(公告)号：US20060236186A1

公开(公告)日：2006-10-19

申请号：US11276771

申请日：2006-03-14

Applicant: Seongmoon Wang ,  Kedarnath Balakrishnan ,  Srimat Chakradhar

Inventor： Seongmoon Wang ,  Kedarnath Balakrishnan ,  Srimat Chakradhar

IPC: G01R31/28 ,  G06F11/00

CPC classification number: G01R31/318335 ,  G01R31/3181

Abstract: A test output compaction arrangement and a method of generating control patterns for unknown blocking is herein disclosed. The specified bits in the control patterns, which when using linear feedback shift register (LFSR) reseeding determines control data volume and LFSR size, are preferably organized in a manner so as to balance the number of specified bits in the control patterns across test patterns.

Abstract translation: 本文公开了测试输出压缩装置和产生未知阻塞的控制模式的方法。 当使用线性反馈移位寄存器（LFSR）重新进给确定控制数据量和LFSR大小时，控制模式中的指定位优选地以使得跨越测试模式平衡控制模式中的指定位的数目的方式来组织。

公开(公告)号：US07730373B2

公开(公告)日：2010-06-01

申请号：US11839190

申请日：2007-08-15

Applicant: Zhanglei Wang ,  Seongmoon Wang

Inventor： Zhanglei Wang ,  Seongmoon Wang

IPC: G01R31/28

CPC classification number: G06F11/2236

Abstract: A method includes obtaining an equivalent core of multiple cores in a System-on-Chip circuit, and applying linear-feedback shift register LFSR reseeding for compressing test data of the equivalent core.

Abstract translation: 一种方法包括在片上系统电路中获得多个核心的等效核心，以及应用线性反馈移位寄存器LFSR重新进给来压缩等效核心的测试数据。

公开(公告)号：US20100121585A1

公开(公告)日：2010-05-13

申请号：US12393533

申请日：2009-02-26

Applicant: Seongmoon Wang ,  Xiangyu Tang

Inventor： Seongmoon Wang ,  Xiangyu Tang

IPC: G01R31/00 ,  G06F19/00

CPC classification number: G01R31/318547

Abstract: According to exemplary methods and systems of the present principles, the location of defective field repairable units (FRUS) of a circuit that have varying sizes or varying numbers of scan cells may be identified by employing tiles including scan cells from different FRUS. A set of test patterns may be scanned through the scan cells such that cells belonging to FRUs within a tile may be concealed while analyzing the response of scan cells in the tile contributed by a different FRU. Further, defective tiles are discoverable at any tile location and in any quantity within a maximal capacity using a compressed signature. In addition, signature registers that process data at a rate that is faster than the scan shift rate of the circuit may be employed during compression to multiply a circuit response by a plurality of components of a compression matrix during one scan shift cycle.

Abstract translation: 根据本原理的示例性方法和系统，可以通过使用包括来自不同FRUS的扫描单元的瓦片来识别具有不同大小或不同数目的扫描单元的电路的缺陷现场修复单元（FRUS）的位置。 可以通过扫描单元扫描一组测试图案，使得属于瓦片内的FRU的单元可以被隐藏，同时分析由不同FRU贡献的瓦片中的扫描单元的响应。 此外，在任何瓦片位置和使用压缩签名的最大容量内的任何数量中都可以发现有缺陷的瓦片。 此外，在压缩期间可以采用以比电路的扫描偏移速率更快的速率处理数据的签名寄存器，以在一个扫描移位周期期间乘以压缩矩阵的多个分量的电路响应。

公开(公告)号：US20090119556A1

公开(公告)日：2009-05-07

申请号：US12265330

申请日：2008-11-05

Applicant: Kedarnath Balakrishnan ,  Seongmoon Wang ,  Wenlong Wei ,  Srimat T. Chakradhar

Inventor： Kedarnath Balakrishnan ,  Seongmoon Wang ,  Wenlong Wei ,  Srimat T. Chakradhar

IPC: G01R31/3177 ,  G06F11/25

CPC classification number: G01R31/31921

Abstract: Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor is configured to generate a test pattern from the seed and the locations of scan inputs. The decompressor includes a first test pattern generator, a second test pattern generator, and a selector configured to select the test pattern generated by the first test pattern generator or the test pattern generated by the second test pattern generator using the locations of scan inputs.

Abstract translation: 公开了一种包括解压缩器和与解压缩器通信的测试器的逻辑测试系统。 测试器被配置为存储种子和扫描输入的位置，并且还被配置为将种子和扫描输入的位置传送到解压缩器。 解压缩器被配置为从种子和扫描输入的位置生成测试图案。 解压缩器包括第一测试图案发生器，第二测试图案发生器和被配置为选择由第一测试图案发生器生成的测试图案或由第二测试图案发生器使用扫描输入位置产生的测试图案的选择器。