公开(公告)号：US08654108B2

公开(公告)日：2014-02-18

申请号：US13393812

申请日：2010-04-13

申请人： Shinya Tanaka ,  Tetsuo Kikuchi ,  Junya Shimada ,  Takuya Watanabe

发明人： Shinya Tanaka ,  Tetsuo Kikuchi ,  Junya Shimada ,  Takuya Watanabe

IPC分类号： G09G5/00 ,  G06F3/038

CPC分类号： G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2310/0286

摘要： In a liquid crystal display device provided with a monolithic gate driver, a panel frame area is to be reduced as compared with a conventional configuration so that the device size can be reduced. In a region on an array substrate located outside of a display region, a third metal (503) is formed as a metal film in addition to a source metal (501) and a gate metal (502). The source metal (501) forms a wiring pattern that includes source electrodes of thin film transistors disposed in a pixel circuit and a gate driver, and the gate metal (502) forms a wiring pattern that includes gate electrodes of the thin film transistors. The third metal (503) is electrically connected to at least one of the source metal (501) and the gate metal (502) through a contact.

摘要翻译： 在具有单片栅极驱动器的液晶显示装置中，与传统的结构相比，面板框架区域将被减小，从而可以减小装置的尺寸。 在位于显示区域外部的阵列基板上的区域中，除了源极金属（501）和栅极金属（502）之外，还形成第三金属（503）作为金属膜。 源极金属（501）形成包括设置在像素电路中的薄膜晶体管的源电极和栅极驱动器的布线图案，并且栅极金属（502）形成包括薄膜晶体管的栅电极的布线图案。 第三金属（503）通过触点与源极金属（501）和栅极金属（502）中的至少一个电连接。

公开(公告)号：US20120162179A1

公开(公告)日：2012-06-28

申请号：US13393812

申请日：2010-04-13

申请人： Shinya Tanaka ,  Tetsuo Kikuchi ,  Junya Shimada ,  Takuya Watanabe

发明人： Shinya Tanaka ,  Tetsuo Kikuchi ,  Junya Shimada ,  Takuya Watanabe

IPC分类号： G09G5/00 ,  G09G3/36

CPC分类号： G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2310/0286

摘要： In a liquid crystal display device provided with a monolithic gate driver, a panel frame area is to be reduced as compared with a conventional configuration so that the device size can be reduced. In a region on an array substrate located outside of a display region, a third metal (503) is formed as a metal film in addition to a source metal (501) and a gate metal (502). The source metal (501) forms a wiring pattern that includes source electrodes of thin film transistors disposed in a pixel circuit and a gate driver, and the gate metal (502) forms a wiring pattern that includes gate electrodes of the thin film transistors. The third metal (503) is electrically connected to at least one of the source metal (501) and the gate metal (502) through a contact.

摘要翻译： 在具有单片栅极驱动器的液晶显示装置中，与传统的结构相比，面板框架区域将被减小，从而可以减小装置的尺寸。 在位于显示区域外部的阵列基板上的区域中，除了源极金属（501）和栅极金属（502）之外，还形成第三金属（503）作为金属膜。 源极金属（501）形成包括设置在像素电路中的薄膜晶体管的源电极和栅极驱动器的布线图案，并且栅极金属（502）形成包括薄膜晶体管的栅电极的布线图案。 第三金属（503）通过触点与源极金属（501）和栅极金属（502）中的至少一个电连接。

公开(公告)号：US09029861B2

公开(公告)日：2015-05-12

申请号：US13809930

申请日：2011-05-20

申请人： Tetsuo Kikuchi ,  Yoshiharu Kataoka ,  Shinya Tanaka ,  Junya Shimada ,  Chikao Yamasaki

发明人： Tetsuo Kikuchi ,  Yoshiharu Kataoka ,  Shinya Tanaka ,  Junya Shimada ,  Chikao Yamasaki

IPC分类号： H01L29/10 ,  H01L29/76 ,  H01L31/036 ,  H01L31/112 ,  H01L29/786 ,  H01L27/12 ,  H01L27/02

CPC分类号： H01L29/78696 ,  H01L27/0207 ,  H01L27/12 ,  H01L27/1222 ,  H01L27/1225 ,  H01L29/7869

摘要： Thin film transistors having a high current drive capability and a suitable threshold voltage are provided. The thin film transistor includes a gate electrode, an insulating layer formed on the gate electrode, a semiconductor layer formed on the insulating layer, and source/drain electrodes formed on the semiconductor layer. The semiconductor layer includes a plurality of regions separated from each other in a longitudinal direction of the source/drain electrodes.

摘要翻译： 提供具有高电流驱动能力和合适阈值电压的薄膜晶体管。 薄膜晶体管包括栅电极，形成在栅电极上的绝缘层，形成在绝缘层上的半导体层以及形成在半导体层上的源/漏电极。 半导体层包括在源极/漏极的纵向彼此分离的多个区域。

公开(公告)号：US08781059B2

公开(公告)日：2014-07-15

申请号：US13637367

申请日：2011-01-06

申请人： Tetsuo Kikuchi ,  Shinya Tanaka ,  Junya Shimada ,  Chikao Yamasaki

发明人： Tetsuo Kikuchi ,  Shinya Tanaka ,  Junya Shimada ,  Chikao Yamasaki

IPC分类号： G11C19/00

CPC分类号： G11C19/184 ,  G09G3/3677 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/28

摘要： A shift register is formed by connecting unit circuits 11 in multi-stage. One electrode of a capacitor Cap2 in the unit circuit 11 is connected to the gate terminal (node N1) of a transistor T2, and the other connected to a node N2. A compensation circuit composed of transistors T3 to T5 provides a clock signal CKB to the node N2 when the node N1 potential is at low level, and applies a low-level potential to the node N2 when the node N1 potential is at high level. Accordingly, even when the gate potential of the transistor T2 changes with a change in a clock signal CK, a signal that cancels out the change is provided through the capacitor Cap2, stabilizing the gate potential of the transistor T2. Thus, a change in the control terminal potential of an output transistor associated with a change in a clock signal is prevented.

摘要翻译： 通过多级连接单元电路11形成移位寄存器。 单元电路11中的电容器Cap2的一个电极连接到晶体管T2的栅极端子（节点N1），另一个连接到节点N2。 当晶体管T3至T5组成的补偿电路在节点N1电位处于低电平时向节点N2提供时钟信号CKB，并且当节点N1电位处于高电平时向节点N2施加低电平电位。 因此，即使当晶体管T2的栅极电位随着时钟信号CK的变化而变化时，通过电容器Cap2提供抵消变化的信号，从而稳定晶体管T2的栅极电位。 因此，防止与时钟信号的变化相关联的输出晶体管的控制端电位的变化。

公开(公告)号：US08742424B2

公开(公告)日：2014-06-03

申请号：US13511661

申请日：2010-07-09

申请人： Chikao Yamasaki ,  Tetsuo Kikuchi ,  Shinya Tanaka ,  Junya Shimada

发明人： Chikao Yamasaki ,  Tetsuo Kikuchi ,  Shinya Tanaka ,  Junya Shimada

IPC分类号： H01L29/04

CPC分类号： H01L27/124 ,  G09G3/3266 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0286 ,  G11C19/184 ,  G11C19/28 ,  H01L29/41733 ,  H01L29/42384

摘要： The present invention provides a shift register and a display device, each of which operates stably. The present invention relate to a shift register, comprising a thin-film transistor which includes a source electrode, a drain electrode, and a gate electrode, the thin-film transistor being a bottom gate thin-film transistor which includes a comb-shaped source/drain structure, the gate electrode being provided with at least one of a cut and an opening in at least one of a region overlapping with the source electrode and a region overlapping with the drain electrode.

摘要翻译： 本发明提供了一种移位寄存器和显示装置，每个都能稳定地工作。 本发明涉及一种移位寄存器，包括一个薄膜晶体管，它包括一个源电极，一个漏电极和一个栅电极，该薄膜晶体管是一个底栅薄膜晶体管，它包括一个梳形源 漏极结构，栅电极在与源电极重叠的区域和与漏电极重叠的区域中的至少一个区域中设置有切割开口和开口中的至少一个。

公开(公告)号：US08575620B2

公开(公告)日：2013-11-05

申请号：US13697148

申请日：2011-01-25

申请人： Chikao Yamasaki ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Junya Shimada

发明人： Chikao Yamasaki ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Junya Shimada

IPC分类号： H01L27/14

CPC分类号： H05K1/18 ,  G02F1/13454 ,  H01L27/1225 ,  H01L27/1251 ,  H05K7/00

摘要： The present invention provides a circuit board with a reduced circuit area, and a display device comprising the circuit board and a narrower picture frame. The circuit board of the present invention comprises: a bottom gate thin film transistor comprising a first semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode; and a top gate thin film transistor comprising a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode, wherein the first semiconductor layer and the second semiconductor layer are formed from the same material, and the first drain electrode or the first source electrode and the second gate electrode are connected without interposing any other thin film transistor therebetween, and have the same electric potential.

摘要翻译： 本发明提供一种具有减小电路面积的电路板，以及包括电路板和较窄图像帧的显示装置。 本发明的电路板包括：底栅薄膜晶体管，包括第一半导体层，第一栅电极，第一源电极和第一漏电极; 以及包括第二半导体层，第二栅电极，第二源电极和第二漏电极的顶栅薄膜晶体管，其中所述第一半导体层和所述第二半导体层由相同的材料形成，并且所述第一漏极 电极或第一源电极和第二栅极电极连接而不在其间插入任何其它薄膜晶体管，并且具有相同的电位。

公开(公告)号：US08559588B2

公开(公告)日：2013-10-15

申请号：US13264828

申请日：2009-12-25

申请人： Tetsuo Kikuchi ,  Shinya Tanaka ,  Chikao Yamasaki ,  Junya Shimada

发明人： Tetsuo Kikuchi ,  Shinya Tanaka ,  Chikao Yamasaki ,  Junya Shimada

IPC分类号： G11C19/00

CPC分类号： G09G3/20 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2330/021 ,  G11C19/28

摘要： Provided is a shift register configured by cascade connecting unit circuits each including a bootstrap circuit. In at least one example embodiment, for the unit circuits, a time period during which a transistor is in an ON state and a clock signal is high level corresponds to a clock passing period. Among transistors whose one conduction terminal is connected to a gate of the transistor, channel lengths of transistors configured such that a low-level potential is fed to gates of the transistors to turn the transistors to an OFF state in the clock passing period and that a low-level potential is applied to the conduction terminal of the transistors in the clock passing period are made longer than the channel length of the transistor. With this, it is possible to reduce a leakage current in the clock passing period, and to prevent the fluctuation of a gate potential of the transistor and dullness in an output signal from occurring.

摘要翻译： 提供一种移位寄存器，其通过级联连接单元电路来构成，每个单元电路包括自举电路。 在至少一个示例性实施例中，对于单元电路，晶体管处于导通状态和时钟信号为高电平的时间段对应于时钟传递周期。 在其一个导通端子连接到晶体管的栅极的晶体管中，晶体管的沟道长度被配置为使得低电平电位被馈送到晶体管的栅极，以在晶体管的时钟通过期间将晶体管转换为截止状态，并且 在晶体管的导通端子中施加低电位电位使晶体管的通过时间长于晶体管的沟道长度。 由此，可以减小时钟通过期间的漏电流，并且防止晶体管的栅极电位的波动和输出信号中的钝度发生。

公开(公告)号：US20130092927A1

公开(公告)日：2013-04-18

申请号：US13639138

申请日：2011-01-17

申请人： Atsuhito Murai ,  Shinya Tanaka ,  Hideki Kitagawa ,  Hajime Imai ,  Mitsunori Imade ,  Tetsuo Kikuchi ,  Kazunori Morimoto ,  Junya Shimada ,  Jun Nishimura

发明人： Atsuhito Murai ,  Shinya Tanaka ,  Hideki Kitagawa ,  Hajime Imai ,  Mitsunori Imade ,  Tetsuo Kikuchi ,  Kazunori Morimoto ,  Junya Shimada ,  Jun Nishimura

IPC分类号： H01L27/15

CPC分类号： H01L27/15 ,  G02F1/13318 ,  G02F1/13338 ,  G02F1/136204 ,  G02F1/1368 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1251 ,  H01L29/42384 ,  H01L29/78633 ,  H01L29/7869

摘要： The circuit board (1) of the present invention includes a plurality of transistor elements provided on a single insulating substrate (2) for respective pixels that are two-dimensionally arranged or respective pixels in a group of a predetermined number of the pixels. At least one of the plurality of transistor elements is an oxide TFT (10) having a channel layer (11) formed by an oxide semiconductor, and at least another of the plurality of transistor elements is an a-Si TFT (20) having a channel layer (21) formed by, for example, an amorphous silicon semiconductor. Each of the oxide TFT (10) and the a-Si TFT (20) is a bottom-gate transistor.

摘要翻译： 本发明的电路板（1）包括设置在单个绝缘基板（2）上的多个晶体管元件，用于各个像素的二维排列或者在一组预定数量的像素中的各个像素。 多个晶体管元件中的至少一个是具有由氧化物半导体形成的沟道层（11）的氧化物TFT（10），并且多个晶体管元件中的至少另一个是具有 沟道层（21）由例如非晶硅半导体形成。 氧化物TFT（10）和a-Si TFT（20）中的每一个都是底栅晶体管。

公开(公告)号：US09111810B2

公开(公告)日：2015-08-18

申请号：US13643652

申请日：2011-03-02

申请人： Hideki Kitagawa ,  Shinya Tanaka ,  Hajime Imai ,  Atsuhito Murai ,  Mitsunori Imade ,  Tetsuo Kikuchi ,  Kazunori Morimoto ,  Junya Shimada ,  Jun Nishimura

发明人： Hideki Kitagawa ,  Shinya Tanaka ,  Hajime Imai ,  Atsuhito Murai ,  Mitsunori Imade ,  Tetsuo Kikuchi ,  Kazunori Morimoto ,  Junya Shimada ,  Jun Nishimura

IPC分类号： H01L29/10 ,  H01L29/12 ,  H01L27/12 ,  H01L27/146 ,  H01L27/144

CPC分类号： H01L27/1251 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/1446 ,  H01L27/14632 ,  H01L27/14678

摘要： A circuit board (1) includes a plurality of transistor elements on an insulating substrate (2). At least one of the plurality of transistor elements is an oxide TFT (10) including, as a channel layer (11), an oxide semiconductor. At least one of the plurality of transistor elements is an a-SiTFT (20) (i) being different from the oxide TFT (10) in functions as circuit components and (ii) including, as a channel layer (21), an amorphous silicon semiconductor. The oxide TFT (10) is a top gate transistor, and the a-SiTFT (20) is a bottom gate transistor. This provides: a configuration that can (a) enhance the performance of the circuit board equipped with the TFTs differing in their respective functions as circuit components and (b) reduce the area necessary for mounting the TFTs; and a method for producing the circuit board.

摘要翻译： 电路板（1）在绝缘基板（2）上包括多个晶体管元件。 多个晶体管元件中的至少一个是氧化物TFT（10），其包括作为沟道层（11）的氧化物半导体。 多个晶体管元件中的至少一个是与作为电路元件的功能的氧化物TFT（10）不同的a-SiTFT（20）（i），（ii）包括作为沟道层（21）的无定形 硅半导体。 氧化物TFT（10）是顶栅晶体管，并且a-SiTFT（20）是底栅晶体管。 这提供：一种配置，其可以（a）增强配备有作为电路部件的各自功能不同的TFT的电路板的性能，（b）减小安装TFT所需的面积; 以及电路基板的制造方法。

公开(公告)号：US08786582B2

公开(公告)日：2014-07-22

申请号：US13504133

申请日：2010-06-02

申请人： Junya Shimada ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Chikao Yamasaki

发明人： Junya Shimada ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Chikao Yamasaki

IPC分类号： G09G5/00 ,  G02F1/1345

CPC分类号： G02F1/13452 ,  G02F1/13454

摘要： The present invention is to provide a display panel and a display apparatus which can reduce the picture-frame area while sufficiently preventing the delay of signals by allowing a required amount of current to flow. The display panel of the present invention is a display panel which includes a circuit substrate, and an opposed substrate facing the circuit substrate, and which is featured in that the circuit section is arranged in the picture-frame area of the display panel, in that the circuit section includes trunk wiring, and branch wiring connected to the gate electrode or the source electrode of a transistor in the circuit section, and in that all or a part of the trunk wiring is provided on the opposed substrate, and the branch wiring is provided on the circuit substrate so as to be electrically connected to the trunk wiring via a conductor.

摘要翻译： 本发明提供一种显示面板和显示装置，其能够通过允许所需量的电流流动来充分防止信号的延迟，从而减小画面区域。 本发明的显示面板是包括电路基板和面对电路基板的相对基板的显示面板，其特征在于，电路部分布置在显示面板的图像框区域中，其中 电路部分包括主干布线和连接到电路部分中的晶体管的栅电极或源电极的分支布线，并且所述干线布线的全部或一部分设置在相对的基板上，分支布线为 设置在电路基板上，以经由导体与主干布线电连接。