公开(公告)号：US10903838B1

公开(公告)日：2021-01-26

申请号：US16656867

申请日：2019-10-18

Applicant: Silicon Laboratories Inc.

Inventor： Brian Taylor Brunn ,  Paul Ivan Zavalney ,  Adrianus Josephus Bink ,  Chester Yu

IPC: G06F1/08 ,  G06F1/324 ,  H03K19/00

Abstract: An integrated circuit includes a clock management unit that selectively provides a clock signal, an energy management circuit that provides an internal power supply voltage to an internal voltage rail in response to an external power supply voltage, and has a capacitor coupled between the internal voltage rail and a reference voltage terminal, and a clocked digital circuit that is coupled to the internal voltage rail and the reference voltage terminal and operates in synchronism with the clock signal. The clock management unit provides the clock signal at a first frequency during a standby state, continuously at a second frequency higher than the first frequency during an active state, and during a first clock cycle following an end of the standby state while suppressing the clock signal during at least one subsequent clock cycle during a transition state between the standby state and the active state.

公开(公告)号：US20210184657A1

公开(公告)日：2021-06-17

申请号：US16710981

申请日：2019-12-11

Applicant: Silicon Laboratories Inc.

Inventor： Chester Yu

IPC: H03K3/037 ,  H03K19/20

Abstract: An apparatus includes an asynchronous D-latch. The asynchronous D-latch includes a first inverter and a second inverter coupled in an anti-parallel fashion. The asynchronous D-latch further includes a third inverter coupled to provide a complement of a data (D) input signal of the asynchronous D-latch to the first and second inverters. The asynchronous D-latch further includes a meta-stability filter coupled to the first and second inverters.

公开(公告)号：US10944388B1

公开(公告)日：2021-03-09

申请号：US16710365

申请日：2019-12-11

Applicant: Silicon Laboratories Inc.

Inventor： Chester Yu ,  Y Hao Lim

IPC: H03K5/135 ,  H03K19/00 ,  H03K3/012 ,  H03K3/037

Abstract: Improved clock gating cells and related methods are provided. The clock gating cells include a first mutually exclusive element (ME1), a first inverter and a second mutually exclusive element (ME2). ME1 receives a clock input and an enable signal, which is asynchronous to the clock input, and outputs the enable signal based on a timing relationship between the clock input and the enable signal. The first inverter receives the enable signal output from ME1 and provides an inverted enable signal to ME2. ME2 receives the clock input and the inverted enable signal, and provides a clock output based on a timing relationship between the clock input and the inverted enable signal. Together, ME1 and ME2 resolve meta-stability and eliminate glitches in the clock output by preventing rising and falling edges of the enable signal from passing through the mutually exclusive elements during active phases of the clock input.

公开(公告)号：US10601369B2

公开(公告)日：2020-03-24

申请号：US16032348

申请日：2018-07-11

Applicant: SILICON LABORATORIES INC.

Inventor： Tiago Marques ,  Chester Yu

IPC: H03B5/06 ,  H03L3/00 ,  H03B5/36

Abstract: An oscillation circuit including a crystal interface, a crystal amplifier, a level detector, a timing circuit, and a controller. When activated, the crystal amplifier drives a crystal coupled to the crystal interface to establish oscillation, and the level detector indicates when a target amplitude is detected. The controller activates the crystal amplifier and uses the timing circuit and the level detector to measure a startup time of oscillation. The measured startup time is used in calculating a wake up time from a sleep mode in time to perform an operation at a scheduled time. The startup time may be adjusted or averaged and may be remeasured with temperature change. A method of minimizing startup time of a crystal oscillator includes measuring startup time for determining a delay value for programming a wakeup circuit. Robust startup settings may be used in the event of startup failure due to a sleepy crystal.

公开(公告)号：US10056899B1

公开(公告)日：2018-08-21

申请号：US15629318

申请日：2017-06-21

Applicant: Silicon Laboratories Inc.

Inventor： Kenneth W. Fernald ,  Chester Yu ,  Hegong Wei

IPC: H03K3/017 ,  H03K17/687 ,  H03K5/159 ,  H03K19/20 ,  H03K5/05

CPC classification number: H03K5/05 ,  H03K5/12 ,  H03K5/159 ,  H03K19/0016 ,  H03K19/20

Abstract: A signal gating circuit includes a logic circuit that receives a stop signal and an input signal and provides an intermediate signal in response, and a pulse stretcher. The pulse stretcher provides an output signal with no pulse when a width of a pulse of the intermediate signal is less than a first amount, with a pulse having a first pulse width that begins after a start of the pulse of the intermediate signal and ends at a predetermined delay thereafter when a pulse width of the intermediate signal is greater than the first amount but less than a second amount, and with a pulse having a second pulse width that begins after the start of the pulse of the intermediate signal and ends after an end of the pulse of the intermediate signal when a pulse width of the intermediate signal is greater than the second amount.