公开(公告)号：US10903838B1

公开(公告)日：2021-01-26

申请号：US16656867

申请日：2019-10-18

Applicant: Silicon Laboratories Inc.

Inventor： Brian Taylor Brunn ,  Paul Ivan Zavalney ,  Adrianus Josephus Bink ,  Chester Yu

IPC: G06F1/08 ,  G06F1/324 ,  H03K19/00

Abstract: An integrated circuit includes a clock management unit that selectively provides a clock signal, an energy management circuit that provides an internal power supply voltage to an internal voltage rail in response to an external power supply voltage, and has a capacitor coupled between the internal voltage rail and a reference voltage terminal, and a clocked digital circuit that is coupled to the internal voltage rail and the reference voltage terminal and operates in synchronism with the clock signal. The clock management unit provides the clock signal at a first frequency during a standby state, continuously at a second frequency higher than the first frequency during an active state, and during a first clock cycle following an end of the standby state while suppressing the clock signal during at least one subsequent clock cycle during a transition state between the standby state and the active state.

公开(公告)号：US11995007B1

公开(公告)日：2024-05-28

申请号：US17990178

申请日：2022-11-18

Applicant: Silicon Laboratories Inc.

Inventor： Paul Ivan Zavalney ,  Rejoy Roy Mathews

IPC: G06F13/16 ,  G06F13/38

CPC classification number: G06F13/1605 ,  G06F13/1694 ,  G06F13/387

Abstract: A multi-bus protocol memory controller is disclosed. The memory controller utilizes shim circuits to translate between the various bus protocols used in the System on a Chip (SoC) and the bus protocol used by the memory controller. The use of shim circuits reduces the number of bridges required in the SoC and also increases performance. The memory controller is designed such that it may interface with any bus protocol, requiring only the design and inclusion of a shim circuit for that bus protocol.

公开(公告)号：US20170139844A1

公开(公告)日：2017-05-18

申请号：US14943912

申请日：2015-11-17

Applicant: SILICON LABORATORIES INC.

Inventor： Paul Ivan Zavalney ,  Thomas S. David

IPC: G06F12/14

CPC classification number: G06F12/1441 ,  G06F12/1483 ,  G06F2212/1052

Abstract: A computing system includes a central processing unit (CPU) connected to communicate over a bus, a memory configured to have at least three accessible memory storage areas arranged asymmetrically and a memory protection unit (MPU) that receives and controls memory access requests received from the central processing unit and from other processing devices, blocks or processes. The MPU determines, based on an identity of the device, block or process that generated the memory access request, whether to allow access based upon which memory area is being accessed and a type of access being requested. The areas of memory include read/write for secure and non-secure, read/write for secure only, and read for secure and non-secure but write only for secure.

公开(公告)号：US20240168893A1

公开(公告)日：2024-05-23

申请号：US17990178

申请日：2022-11-18

Applicant: Silicon Laboratories Inc.

Inventor： Paul Ivan Zavalney ,  Rejoy Roy Mathews

IPC: G06F13/16 ,  G06F13/38

CPC classification number: G06F13/1605 ,  G06F13/1694 ,  G06F13/387

Abstract: A multi-bus protocol memory controller is disclosed. The memory controller utilizes shim circuits to translate between the various bus protocols used in the System on a Chip (SoC) and the bus protocol used by the memory controller. The use of shim circuits reduces the number of bridges required in the SoC and also increases performance. The memory controller is designed such that it may interface with any bus protocol, requiring only the design and inclusion of a shim circuit for that bus protocol.