公开(公告)号：US20150044821A1

公开(公告)日：2015-02-12

申请号：US14524166

申请日：2014-10-27

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chung-Lun Liu ,  Jung-Pin Huang ,  Yi-Feng Chang ,  Chin-Huang Chang

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L23/3107 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/858 ,  H01L2224/8592 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15321 ,  H01L2924/15323 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire structure and increases the wiring bonding difficultly.

Abstract translation: 提供了一种多芯片堆叠结构及其制造方法。 制造多芯片堆叠结构的方法包括通过使用阶梯状方式将包括多个第一芯片的第一芯片组布置在芯片载体上，将第二芯片设置在第一芯片组的顶部上的第一芯片上， 通过接合线将第一芯片组和第二芯片电连接到芯片载体上，使用薄膜覆盖线（FOW）来在第一芯片和第二芯片之间设置绝缘膜，其中绝缘膜覆盖部分 在第一组的顶部和第二芯片的至少一部分上的第一芯片的接合线的端部，并且通过接合线将第三芯片电连接到芯片载体，从而防止直接布置在第一芯片上 第二芯片的平面尺寸远远小于现有技术中的第一芯片的平面尺寸，这增加了整个结构的高度，并且难以增加布线接合。

公开(公告)号：US09754927B2

公开(公告)日：2017-09-05

申请号：US14524166

申请日：2014-10-27

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chung-Lun Liu ,  Jung-Pin Huang ,  Yi-Feng Chang ,  Chin-Huang Chang

IPC: H01L29/15 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L23/3107 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/858 ,  H01L2224/8592 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15321 ,  H01L2924/15323 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire structure and increases the wiring bonding difficultly.