公开(公告)号：US20150044821A1

公开(公告)日：2015-02-12

申请号：US14524166

申请日：2014-10-27

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chung-Lun Liu ,  Jung-Pin Huang ,  Yi-Feng Chang ,  Chin-Huang Chang

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L23/3107 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/858 ,  H01L2224/8592 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15321 ,  H01L2924/15323 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire structure and increases the wiring bonding difficultly.

Abstract translation: 提供了一种多芯片堆叠结构及其制造方法。 制造多芯片堆叠结构的方法包括通过使用阶梯状方式将包括多个第一芯片的第一芯片组布置在芯片载体上，将第二芯片设置在第一芯片组的顶部上的第一芯片上， 通过接合线将第一芯片组和第二芯片电连接到芯片载体上，使用薄膜覆盖线（FOW）来在第一芯片和第二芯片之间设置绝缘膜，其中绝缘膜覆盖部分 在第一组的顶部和第二芯片的至少一部分上的第一芯片的接合线的端部，并且通过接合线将第三芯片电连接到芯片载体，从而防止直接布置在第一芯片上 第二芯片的平面尺寸远远小于现有技术中的第一芯片的平面尺寸，这增加了整个结构的高度，并且难以增加布线接合。

公开(公告)号：US08802507B2

公开(公告)日：2014-08-12

申请号：US13667704

申请日：2012-11-02

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Cheng-Chia Chiang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Jung-Pin Huang

IPC: H01L21/78 ,  H01L21/784 ,  H01L21/56 ,  H01L23/433 ,  H01L23/31 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/4334 ,  H01L21/486 ,  H01L23/31 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/81

Abstract: A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.

Abstract translation: 提供了一种半导体封装器件，半导体封装结构及其制造方法，其主要包括在形成有TSV（透硅通孔）的晶片上设置多个半导体芯片，并将半导体芯片与TSV电连接; 用密封剂封装半导体芯片; 并将硬组分设置在密封剂上。 硬组件确保了在焊料凸块工艺期间晶片的平整度，并且在单独化处理期间提供对晶片的支撑，使得晶片可以牢固地位于单个载体上，从而克服现有技术的缺点，即难以安装焊料 碰撞，切割晶片难度大。

公开(公告)号：US09754927B2

公开(公告)日：2017-09-05

申请号：US14524166

申请日：2014-10-27

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chung-Lun Liu ,  Jung-Pin Huang ,  Yi-Feng Chang ,  Chin-Huang Chang

IPC: H01L29/15 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L23/3107 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/858 ,  H01L2224/8592 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15321 ,  H01L2924/15323 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire structure and increases the wiring bonding difficultly.

公开(公告)号：US09058971B2

公开(公告)日：2015-06-16

申请号：US13905703

申请日：2013-05-30

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chih-Yuan Shih ,  Shih-Liang Peng ,  Jung-Pin Huang ,  Chin-Yu Ku ,  Hsien-Wen Chen

IPC: H01L27/15 ,  H01L29/26 ,  H01L31/12 ,  H01L33/00 ,  H01L25/00 ,  H01S5/022 ,  H01S5/024 ,  H01S5/062 ,  H01S5/42

CPC classification number: H01L25/00 ,  H01L2224/48091 ,  H01S5/02252 ,  H01S5/0226 ,  H01S5/02276 ,  H01S5/02288 ,  H01S5/02469 ,  H01S5/06226 ,  H01S5/423 ,  H01L2924/00014

Abstract: An electro-optical module is provided, which includes: a substrate having a first surface with a groove and an opposite second surface; a plurality of support members disposed on the first surface of the substrate; at least an electro-optical element having opposite active and non-active surfaces and disposed in the groove of the substrate via the non-active surface thereof; an interposer disposed on the first surface of the substrate and the electro-optical element for electrically connecting the electro-optical element to the substrate, wherein the interposer has a through hole corresponding in position to the active surface of the electro-optical element; and a transparent plate disposed over the first surface of the substrate and the interposer through the support members and having a lens portion corresponding in position to the through hole of the interposer, thereby reducing signal losses, improving alignment precision, and achieving preferred thermal dissipation and EMI shielding effects.

Abstract translation: 提供了一种电光模块，其包括：具有第一表面和第二表面的基板; 设置在所述基板的第一表面上的多个支撑构件; 至少一个电光元件具有相对的有源和非有源表面，并经由其非有效表面设置在衬底的沟槽中; 设置在基板的第一表面上的插入器和用于将电光元件电连接到基板的电光元件，其中插入器具有与电光元件的有源表面相对应的通孔; 以及设置在基板的第一表面上的透明板和穿过支撑构件的中介层，并且具有与插入件的通孔对应的透镜部分，从而减少信号损失，提高对准精度，并实现优选的散热和 EMI屏蔽效果。

公开(公告)号：US20140192832A1

公开(公告)日：2014-07-10

申请号：US13905703

申请日：2013-05-30

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chih-Yuan Shih ,  Shih-Liang Peng ,  Jung-Pin Huang ,  Chin-Yu Ku ,  Hsien-Wen Chen

IPC: H01S5/062

CPC classification number: H01L25/00 ,  H01L2224/48091 ,  H01S5/02252 ,  H01S5/0226 ,  H01S5/02276 ,  H01S5/02288 ,  H01S5/02469 ,  H01S5/06226 ,  H01S5/423 ,  H01L2924/00014

Abstract: An electro-optical module is provided, which includes: a substrate having a first surface with a groove and an opposite second surface; a plurality of support members disposed on the first surface of the substrate; at least an electro-optical element having opposite active and non-active surfaces and disposed in the groove of the substrate via the non-active surface thereof; an interposer disposed on the first surface of the substrate and the electro-optical element for electrically connecting the electro-optical element to the substrate, wherein the interposer has a through hole corresponding in position to the active surface of the electro-optical element; and a transparent plate disposed over the first surface of the substrate and the interposer through the support members and having a lens portion corresponding in position to the through hole of the interposer, thereby reducing signal losses, improving alignment precision, and achieving preferred thermal dissipation and EMI shielding effects.

Abstract translation: 提供了一种电光模块，其包括：具有第一表面和第二表面的基板; 设置在所述基板的第一表面上的多个支撑构件; 至少一个电光元件具有相对的有源和非有源表面，并经由其非有效表面设置在衬底的沟槽中; 设置在基板的第一表面上的插入器和用于将电光元件电连接到基板的电光元件，其中插入器具有与电光元件的有源表面相对应的通孔; 以及设置在基板的第一表面上的透明板和穿过支撑构件的中介层，并且具有与插入件的通孔对应的透镜部分，从而减少信号损失，提高对准精度，并实现优选的散热和 EMI屏蔽效果。