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    MULTI-LAYERED METAL LINE OF SEMICONDUCTOR DEVICE FOR PREVENTING DIFFUSION BETWEEN METAL LINES AND METHOD FOR FORMING THE SAME
    1.
    发明申请
    MULTI-LAYERED METAL LINE OF SEMICONDUCTOR DEVICE FOR PREVENTING DIFFUSION BETWEEN METAL LINES AND METHOD FOR FORMING THE SAME 失效
    用于防止金属线之间的扩散的半导体器件的多层金属线及其形成方法

    公开(公告)号：US20100038788A1

    公开(公告)日：2010-02-18

    申请号：US12607267

    申请日：2009-10-28

    申请人： Jeong Tae KIM ,  Baek Mann KIM ,  Soo Hyun KIM ,  Young Jin LEE ,  Dong Ha JUNG

    发明人： Jeong Tae KIM ,  Baek Mann KIM ,  Soo Hyun KIM ,  Young Jin LEE ,  Dong Ha JUNG

    IPC分类号： H01L23/532

    CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76856 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A multi-layered metal line of a semiconductor device includes a semiconductor substrate; a lower metal line formed on the semiconductor substrate and recessed on a surface thereof; an insulation layer formed on the semiconductor substrate including the lower metal line and having a damascene pattern for exposing a recessed portion of the lower metal line and for delimiting an upper metal line forming region; a glue layer formed on a surface of the recessed portion of the lower metal line; a first diffusion barrier formed on the glue layer to fill the recessed portion of the lower metal line; a second diffusion barrier formed on the glue layer and the first diffusion barrier; a third diffusion barrier formed on the second diffusion barrier and a surface of the damascene pattern; and an upper metal line formed on the third diffusion barrier to fill the damascene pattern.

    摘要翻译： 半导体器件的多层金属线包括半导体衬底; 形成在半导体衬底上并在其表面上凹陷的下金属线; 形成在所述半导体衬底上的绝缘层，所述绝缘层包括所述下金属线并且具有用于暴露所述下金属线的凹陷部分并限定上金属线形成区域的镶嵌图案; 形成在下金属线的凹部的表面上的胶层; 形成在所述胶层上以填充所述下金属线的凹部的第一扩散阻挡层; 形成在所述胶层和所述第一扩散阻挡层上的第二扩散阻挡层; 形成在所述第二扩散阻挡层上的第三扩散阻挡层和所述镶嵌图案的表面; 以及形成在第三扩散阻挡层上以填充镶嵌图案的上金属线。

    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE CAPABLE OF REDUCING PARASITIC BIT LINE CAPACITANCE
    8.
    发明申请
    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE CAPABLE OF REDUCING PARASITIC BIT LINE CAPACITANCE 失效
    制造可降低PARASITIC BIT线电容的半导体器件的方法

    公开(公告)号：US20080146026A1

    公开(公告)日：2008-06-19

    申请号：US11776905

    申请日：2007-07-12

    申请人： Soo Hyun KIM ,  Baek Mann KIM ,  Young Jin LEE ,  Sun Woo HWANG ,  Dong Ha JUNG ,  Jeong Tae KIM

    发明人： Soo Hyun KIM ,  Baek Mann KIM ,  Young Jin LEE ,  Sun Woo HWANG ,  Dong Ha JUNG ,  Jeong Tae KIM

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76826 ,  H01L21/76838 ,  H01L27/10885 ,  H01L27/10888

    摘要： A semiconductor memory device is manufactured by: forming a hole by etching an interlayer insulation film formed over a semiconductor substrate; forming a barrier film over the interlayer insulation film including a surface of the hole; forming a first metal film over the barrier film so as to fill in the hole; forming a bit line contact plug in the hole by removing the first metal film and the barrier film so as to expose the interlayer insulation film; carrying out a gas treatment to a surface of the interlayer insulation film including the bit line contact plug so as to promote a growth of metal nucreation; forming a second metal film over the gas treated interlayer insulation film; and forming a bit line in contact with the bit line contact plug by etching the second metal film.

    摘要翻译： 半导体存储器件通过：通过蚀刻形成在半导体衬底上的层间绝缘膜来形成孔; 在包括所述孔的表面的所述层间绝缘膜上形成阻挡膜; 在所述阻挡膜上形成第一金属膜以填充所述孔; 通过去除第一金属膜和阻挡膜以形成层间绝缘膜，从而在孔中形成位线接触插塞; 对包含位线接触插塞的层间绝缘膜的表面进行气体处理，以促进金属含量的增长; 在气体处理的层间绝缘膜上形成第二金属膜; 并通过蚀刻第二金属膜形成与位线接触插塞接触的位线。

    METHOD OF FORMING TUNGSTEN POLYMETAL GATE HAVING LOW RESISTANCE
    10.
    发明申请
    METHOD OF FORMING TUNGSTEN POLYMETAL GATE HAVING LOW RESISTANCE 失效
    形成具有低电阻性的钨金属聚合物的方法

    公开(公告)号：US20080081452A1

    公开(公告)日：2008-04-03

    申请号：US11693137

    申请日：2007-03-29

    申请人： Soo Hyun KIM ,  Noh Jung KWAK ,  Baek Mann KIM ,  Young Jin LEE ,  Sun Woo HWANG ,  Kwan Yong LIM

    发明人： Soo Hyun KIM ,  Noh Jung KWAK ,  Baek Mann KIM ,  Young Jin LEE ,  Sun Woo HWANG ,  Kwan Yong LIM

    IPC分类号： H01L21/3205

    CPC分类号： H01L21/28061 ,  H01L29/4941

    摘要： A tungsten polymetal gate is made by forming a gate insulation layer and a polysilicon layer on a semiconductor substrate; depositing a barrier layer on the polysilicon layer; depositing a tungsten nucleation layer on the barrier layer through an ALD process; depositing a tungsten layer on the tungsten nucleation layer through a CVD process; depositing a hard mask layer on the tungsten layer; and etching the hard mask layer, the tungsten layer, the tungsten nucleation layer, the barrier layer, the polysilicon layer, and the gate insulation layer.

    摘要翻译： 通过在半导体衬底上形成栅极绝缘层和多晶硅层来制造钨多金属栅极; 在所述多晶硅层上沉积阻挡层; 通过ALD工艺在阻挡层上沉积钨成核层; 通过CVD工艺在钨成核层上沉积钨层; 在钨层上沉积硬掩模层; 并且蚀刻硬掩模层，钨层，钨成核层，势垒层，多晶硅层和栅极绝缘层。