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47 条记录 (耗时 0.026 秒)

    Method and apparatus for changing data transfer widths in a computer system
    3.
    发明授权
    Method and apparatus for changing data transfer widths in a computer system 失效
    用于在计算机系统中改变数据传输宽度的方法和装置

    公开(公告)号：US5911053A

    公开(公告)日：1999-06-08

    申请号：US723572

    申请日：1996-09-30

    申请人： Stephen S. Pawlowski ,  Peter D. MacWilliams ,  Gurbir Singh

    发明人： Stephen S. Pawlowski ,  Peter D. MacWilliams ,  Gurbir Singh

    IPC分类号： G06F13/40 ,  G06F3/00

    CPC分类号： G06F13/4018

    摘要： In a method and apparatus for changing data transfer widths in a computer system, a first agent on a bus provides a first indication to a second agent on the bus identifying one or more data transfer widths supported by the first agent. The second agent then provides a second indication to the first agent identifying one or more data transfer widths supported by the second agent. A data transfer width is then determined based on the first indication and the second indication. According to an embodiment of the present invention, a third agent involved in a transaction is also able to provide a third indication to the first and/or second agents identifying one or more data transfer widths supported by the third agent. The data transfer width(s) is then determined based on the first, second, and third indications.

    摘要翻译： 在用于改变计算机系统中的数据传输宽度的方法和装置中，总线上的第一代理向总线上的第二代理提供第一指示，以识别第一代理所支持的一个或多个数据传输宽度。 然后，第二代理向第一代理提供识别由第二代理支持的一个或多个数据传输宽度的第二指示。 然后基于第一指示和第二指示确定数据传输宽度。 根据本发明的实施例，参与交易的第三代理还能够向第一代理和/或第二代理提供第三指示，以识别由第三代理支持的一个或多个数据传输宽度。 然后基于第一，第二和第三指示确定数据传送宽度。

    Highly pipelined bus architecture
    4.
    发明授权
    Highly pipelined bus architecture 失效
    高度流水线总线架构

    公开(公告)号：US5796977A

    公开(公告)日：1998-08-18

    申请号：US688238

    申请日：1996-07-29

    申请人： Nitin V. Sarangdhar ,  Gurbir Singh ,  Konrad Lai ,  Stephen S. Pawlowski ,  Peter D. MacWilliams ,  Michael W. Rhodehamel

    发明人： Nitin V. Sarangdhar ,  Gurbir Singh ,  Konrad Lai ,  Stephen S. Pawlowski ,  Peter D. MacWilliams ,  Michael W. Rhodehamel

    IPC分类号： G06F12/08 ,  G06F13/18 ,  G06F12/00 ,  G06F13/00

    CPC分类号： G06F13/18 ,  G06F12/0831

    摘要： A computer system incorporating a pipelined bus that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system includes bus agents having in-order-queues that track multiple outstanding transactions across a system bus and that perform snoops in response to transaction requests providing snoop results and modified data within one transaction. Additionally, the system supports long latency transactions by providing deferred identifiers during transaction requests that are used to restart deferred transactions.

    摘要翻译： 描述了包含维护数据一致性的流水线总线的计算机系统，支持长延迟事务并提供处理器顺序。 计算机系统包括总线代理，其具有在系统总线上跟踪多个未完成事务的按顺序队列，并且响应于在一个事务中提供窥探结果和修改的数据的事务请求来执行窥探。 此外，系统通过在用于重新启动延迟事务的事务请求期间提供延迟标识符来支持长延迟事务。

    Quad pumped bus architecture and protocol
    7.
    发明授权
    Quad pumped bus architecture and protocol 失效
    四泵浦总线架构和协议

    公开(公告)号：US06807592B2

    公开(公告)日：2004-10-19

    申请号：US09925691

    申请日：2001-08-10

    申请人： Gurbir Singh ,  Robert J. Greiner ,  Stephen S. Pawlowski ,  David L. Hill ,  Donald D. Parker

    发明人： Gurbir Singh ,  Robert J. Greiner ,  Stephen S. Pawlowski ,  David L. Hill ,  Donald D. Parker

    IPC分类号： G06F1300

    CPC分类号： G06F13/4217

    摘要： A bidirectional multidrop processor bus is connected to a plurality of bus agents. Bus throughput can be increased by operating the bus in a multi pumped signaling mode in which multiple information elements are driven onto a bus by a driving agent at a rate that is a multiple of the frequency of the bus clock. The driving agent also activates a strobe to identify sampling points for the information elements. Information elements for a request can be driven, for example, using a double pumped signaling mode in which two information elements are driven during one bus clock cycle. Data elements for a data line transfer can be driven, for example, using a quad pumped signaling mode in which four data elements are driven during one bus clock cycle. Multiple strobe signals can be temporarily activated in an offset or staggered arrangement to reduce the frequency of the strobe signals. Sampling symmetry can be improved by using only one type of edge (e.g., either the rising edges or the falling edges) of the strobe signals to identify the sampling points.

    摘要翻译： 双向多点处理器总线连接到多个总线代理。 可以通过以多抽头信令模式操作总线来增加总线吞吐量，其中多个信息元素以驱动代理以总线时钟频率的倍数的速率被驱动到总线上。 驱动代理还激活选通以识别信息元素的采样点。 可以例如使用双泵浦信号模式来驱动请求的信息元素，其中在一个总线时钟周期期间驱动两个信息元素。 数据线传输的数据元素例如可以使用四泵浦信号模式来驱动，其中四个数据元件在一个总线时钟周期内被驱动。 可以以偏移或交错布置临时地激活多个选通信号，以减少选通信号的频率。 可以通过仅使用选通信号的一种类型的边缘（例如，上升沿或下降沿）来提高采样对称性，以识别采样点。

    Response and data phases in a highly pipelined bus architecture
    8.
    发明授权
    Response and data phases in a highly pipelined bus architecture 失效
    高度流水线总线架构中的响应和数据阶段

    公开(公告)号：US06804735B2

    公开(公告)日：2004-10-12

    申请号：US09784244

    申请日：2001-02-14

    申请人： Gurbir Singh ,  Robert J. Greiner ,  Stephen S. Pawlowski ,  David L. Hill ,  Donald D. Parker

    发明人： Gurbir Singh ,  Robert J. Greiner ,  Stephen S. Pawlowski ,  David L. Hill ,  Donald D. Parker

    IPC分类号： G06F1300

    CPC分类号： G06F13/4217

    摘要： A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a target ready interface, a set of response interfaces for a set of response signals, and a data bus busy interface, and a bus clock interface for a bus clock signal. The bus agent of this embodiment also includes bus controller logic to track a plurality of transactions comprising a transaction N-1 and a transaction N, the bus controller being capable of asserting the target ready signal for transaction N if the bus agent is asserting the data busy signal for the transaction N-1 and deasserts the data busy signal.

    摘要翻译： 可用于增强的高流水线总线架构中的总线代理。 在一个实施例中，总线代理包括目标就绪接口，用于一组响应信号的一组响应接口和数据总线忙接口以及用于总线时钟信号的总线时钟接口。 该实施例的总线代理还包括总线控制器逻辑以跟踪包括事务N-1和事务N的多个事务，总线控制器能够为事务N断言目标就绪信号，如果总线代理正在断言数据 忙信号用于事务N-1，并取消对数据忙信号的否定。

    Enhanced highly pipelined bus architecture
    10.
    发明授权
    Enhanced highly pipelined bus architecture 失效
    增强高流水线总线架构

    公开(公告)号：US06907487B2

    公开(公告)日：2005-06-14

    申请号：US09783852

    申请日：2001-02-14

    申请人： Gurbir Singh ,  Robert J. Greiner ,  Stephen S. Pawlowski ,  David L. Hill ,  Donald D. Parker

    发明人： Gurbir Singh ,  Robert J. Greiner ,  Stephen S. Pawlowski ,  David L. Hill ,  Donald D. Parker

    IPC分类号： G06F13/36 ,  G06F13/42 ,  G06F13/14

    CPC分类号： G06F13/4217

    摘要： A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a control interface to drive a control signal at a clock frequency, an address bus interface to drive address elements at twice the clock frequency, and a data bus interface to drive data elements at four times the clock frequency. The address bus interface drives a substantially centered address strobe transition for each address element, and the data bus interface drives a substantially centered data strobe transition for each data element.

    摘要翻译： 可用于增强的高流水线总线架构中的总线代理。 在一个实施例中，总线代理包括用于以时钟频率驱动控制信号的控制接口，用于以两倍时钟频率驱动地址元件的地址总线接口和用于以四倍于时钟频率驱动数据元素的数据总线接口 。 地址总线接口为每个地址元件驱动基本中心的地址选通转换，并且数据总线接口为每个数据元件驱动基本中心的数据选通转换。