公开(公告)号：US06601121B2

公开(公告)日：2003-07-29

申请号：US09925692

申请日：2001-08-10

申请人： Gurbir Singh ,  Robert J. Greiner ,  Stephen S. Pawlowski ,  David L. Hill ,  Donald D. Parker

发明人： Gurbir Singh ,  Robert J. Greiner ,  Stephen S. Pawlowski ,  David L. Hill ,  Donald D. Parker

IPC分类号： G06F1300

CPC分类号： G06F13/4217

摘要： A bidirectional multidrop processor bus is connected to a plurality of bus agents. Bus throughput can be increased by operating the bus in a multi pumped signaling mode in which multiple information elements are driven onto a bus by a driving agent at a rate that is a multiple of the frequency of the bus clock. The driving agent also activates a strobe to identify sampling points for the information elements. Information elements for a request can be driven, for example, using a double pumped signaling mode in which two information elements are driven during one bus clock cycle. Data elements for a data line transfer can be driven, for example, using a quad pumped signaling mode in which four data elements are driven during one bus clock cycle. Multiple strobe signals can be temporarily activated in an offset or staggered arrangement to reduce the frequency of the strobe signals. Sampling symmetry can be improved by using only one type of edge (e.g., either the rising edges or the falling edges) of the strobe signals to identify the sampling points.

公开(公告)号：US5822555A

公开(公告)日：1998-10-13

申请号：US716974

申请日：1996-09-20

申请人： Gary L. Brown ,  Donald D. Parker

发明人： Gary L. Brown ,  Donald D. Parker

IPC分类号： G06F9/30

CPC分类号： G06F9/30152 ,  G06F9/3816 ,  G06F9/382

摘要： A circuit and method for supplying and aligning a block of multiple variable length macro instructions to an instruction buffer. Only one cycle is required to align and rotate the block of instruction code. A last byte vector of the instruction code in the instruction buffer is scanned from the last byte in a direction from back to front, thereby saving time. Rotating begins immediately so that a next block of instruction code is available in a next cycle. The block is stored in the instruction buffer after all macroinstructions therein have been steered to the decoder.

摘要翻译： 一种用于将多个可变长度宏指令的块提供和对准到指令缓冲器的电路和方法。 只需一个周期来对齐和旋转指令代码块。 指令缓冲器中的指令代码的最后一个字节向量从最后一个字节沿着从前到前的方向扫描，从而节省时间。 立即开始旋转，以便在下一个周期中下一个指令代码块可用。 在其中的所有宏指令被转向解码器之后，该块被存储在指令缓冲器中。

公开(公告)号：US5600806A

公开(公告)日：1997-02-04

申请号：US204862

申请日：1994-03-01

申请人： Gary L. Brown ,  Donald D. Parker

发明人： Gary L. Brown ,  Donald D. Parker

IPC分类号： G06F9/30 ,  G06F12/04

CPC分类号： G06F9/30152 ,  G06F9/3816 ,  G06F9/382

摘要： A circuit and method for supplying and aligning a block of multiple variable length macro instructions to an instruction buffer. Only one cycle is required to align and rotate the block of instruction code. A last byte vector of the instruction code in the instruction buffer is scanned from the last byte in a direction from back to front, thereby saving time. Rotating begins immediately so that a next block of instruction code is available in a next cycle. The block is stored in the instruction buffer after all macroinstructions therein have been steered to the decoder.

摘要翻译： 一种用于将多个可变长度宏指令的块提供和对准到指令缓冲器的电路和方法。 只需一个周期来对齐和旋转指令代码块。 指令缓冲器中的指令代码的最后一个字节向量从最后一个字节沿着从前到前的方向扫描，从而节省时间。 立即开始旋转，以便在下一个周期中下一个指令代码块可用。 在其中的所有宏指令被转向解码器之后，该块被存储在指令缓冲器中。

公开(公告)号：US5559974A

公开(公告)日：1996-09-24

申请号：US459284

申请日：1995-06-02

申请人： Darrell D. Boggs ,  Gary L. Brown ,  Michael M. Hancock ,  Donald D. Parker

发明人： Darrell D. Boggs ,  Gary L. Brown ,  Michael M. Hancock ,  Donald D. Parker

IPC分类号： G06F9/30 ,  G06F9/35 ,  G06F9/38 ,  G06F9/22

CPC分类号： G06F9/30167 ,  G06F9/30145 ,  G06F9/35 ,  G06F9/3863

摘要： A decoder that includes a micro-alias register to store information from a micro-operation for use by later micro-operations in the micro-operation flow. The decoder includes one or more XLAT PLAs that produces PLA control micro-operations ("Cuops"), a microcode sequencing unit that produces microcode Cuops, and an aliasing mechanism that extracts fields and stores them in macro-alias registers. A multiplexer is provided to select the appropriate Cuop to be stored in a Cuop register. Multiple Cuops may issue each cycle. A multiplexer is coupled to select one of the Cuops and to store predetermined fields in the micro-alias register for use by subsequent Cuops. Micro-alias data and macro-alias data can be utilized simultaneously with a Cuop to form an Auop.

摘要翻译： 一种解码器，其包括微型别名寄存器，用于存储来自微操作的信息以供微操作流中的后续微操作使用。 解码器包括产生PLA控制微操作（“Cuops”）的一个或多个XLAT PLA，产生微代码Cuops的微代码排序单元，以及提取字段并将其存储在宏别名寄存器中的混叠机制。 提供多路复用器以选择要存储在Cuop寄存器中的适当Cuop。 多个Cuops可以发出每个周期。 多路复用器被耦合以选择Cuops中的一个并且将预定字段存储在微别名寄存器中以供随后的Cuops使用。 Micro-alias数据和宏别名数据可以与Cuop同时使用以形成Auop。

公开(公告)号：US06609171B1

公开(公告)日：2003-08-19

申请号：US09474058

申请日：1999-12-29

申请人： Gurbir Singh ,  Robert J. Greiner ,  Stephen S. Pawlowski ,  David L. Hill ,  Donald D. Parker

发明人： Gurbir Singh ,  Robert J. Greiner ,  Stephen S. Pawlowski ,  David L. Hill ,  Donald D. Parker

IPC分类号： G06F112

CPC分类号： G06F13/4217

摘要： A bidirectional multidrop processor bus is connected to a plurality of bus agents. Bus throughput can be increased by operating the bus in a multi pumped signaling mode in which multiple information elements are driven onto a bus by a driving agent at a rate that is a multiple of the frequency of the bus clock. The driving agent also activates a strobe to identify sampling points for the information elements. Information elements for a request can be driven, for example, using a double pumped signaling mode in which two information elements are driven during one bus clock cycle. Data elements for a data line transfer can be driven, for example, using a quad pumped signaling mode in which four data elements are driven during one bus clock cycle. Multiple strobe signals can be temporarily activated in an offset or staggered arrangement to reduce the frequency of the strobe signals. Sampling symmetry can be improved by using only one type of edge (e.g., either the rising edges or the falling edges) of the strobe signals to identify the sampling points.

公开(公告)号：US5673427A

公开(公告)日：1997-09-30

申请号：US675419

申请日：1996-07-03

申请人： Gary L. Brown ,  Adrian L. Carbine ,  Donald D. Parker

发明人： Gary L. Brown ,  Adrian L. Carbine ,  Donald D. Parker

IPC分类号： G06F9/28 ,  G06F9/30 ,  G06F9/38 ,  G06F9/22

CPC分类号： G06F9/30167 ,  G06F9/28 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/383

摘要： A micro-operation queue for holding a plurality of micro-operations supplied simultaneously by a decoder. A plurality of packing multiplexers are coupled to receive the plurality of micro-operations, and valid bits associated therewith, and to provide packed micro-operation data output in which the valid micro-operations are positioned in adjacent outputs, thereby removing all empty slots. A FIFO queue receives the packed data, in responsive to valid micro-operations, stores the valid micro-operations starting with the next available empty queue location. An embodiment described in which the FIFO queue includes a circular queue with a plurality of entries. In one embodiment, alignment multiplexers for the circular queue are combined with the packing multiplexers, to provide a single-level plurality of packing and aligning multiplexers that has a control system that, responsive to the valid bits of the packed data and the next available pointer of the circular queue, packs, aligns, and stores the micro-operations into the circular queue from where they can be issued.

摘要翻译： 一种用于保持由解码器同时提供的多个微操作的微操作队列。 耦合多个封装多路复用器以接收多个微操作以及与其相关联的有效位，并且提供压缩的微操作数据输出，其中有效微操作位于相邻的输出端，从而去除所有的空槽。 FIFO队列接收打包数据，响应于有效的微操作，存储从下一个可用空队列位置开始的有效微操作。 所描述的实施例，其中FIFO队列包括具有多个条目的循环队列。 在一个实施例中，用于循环队列的对准多路复用器与打包多路复用器组合，以提供具有控制系统的单级多个打包和对准多路复用器，该控制系统响应于打包数据的有效位和下一个可用指针 的循环队列，将微操作打包，对齐并存储到可以从其发布的循环队列中。

公开(公告)号：US5586277A

公开(公告)日：1996-12-17

申请号：US479867

申请日：1995-06-07

申请人： Gary L. Brown ,  Donald D. Parker

发明人： Gary L. Brown ,  Donald D. Parker

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/382 ,  G06F9/30152 ,  G06F9/3816 ,  G06F9/3822

摘要： A circuit and method for simultaneously steering multiple aligned macroinstructions from an instruction buffer to a decoder that receives and decodes multiple macroinstructions in parallel. A first macroinstruction is supplied to a first decoder by steering a first predetermined number of bytes following the first buffer byte. A second macroinstruction is supplied by scanning a first opcode byte vector to locate a first opcode byte, and then steering a second predetermined number of bytes beginning at said first opcode to a second decoder. Operations to locate the first byte of each of the macroinstructions and to steer them to the decoders are accomplished in one cycle. If said macroinstruction cannot be decoded by said second decoder, then it is resteered to the first decoder. Steering and resteering operations continue until all complete macroinstructions within the instruction buffer have been accepted by the decoders.

摘要翻译： 一种用于从指令缓冲器同时引导多个对准的宏指令到解码器的电路和方法，该解码器并行地接收和解码多个宏指令。 通过转向第一缓冲区字节之后的第一预定数量的字节来将第一宏指令提供给第一解码器。 通过扫描第一操作码字节向量来定位第一操作码字节，然后将从所述第一操作码开始的第二预定数量的字节转向第二解码器来提供第二宏指令。 定位每个宏指令的第一个字节并将其转向解码器的操作在一个周期内完成。 如果所述宏指令不能由所述第二解码器解码，则将其重新安排到第一解码器。 指导缓冲区内的所有完整宏指令都被解码器接受，继续操作和重新开始操作。

公开(公告)号：US5566298A

公开(公告)日：1996-10-15

申请号：US204744

申请日：1994-03-01

申请人： Darrell D. Boggs ,  Gary L. Brown ,  Michael M. Hancock ,  Donald D. Parker ,  Gail M. Rupnick

发明人： Darrell D. Boggs ,  Gary L. Brown ,  Michael M. Hancock ,  Donald D. Parker ,  Gail M. Rupnick

IPC分类号： G06F9/26 ,  G06F9/38 ,  G06F11/14 ,  G06F11/00 ,  G06F11/20

CPC分类号： G06F11/1407 ,  G06F9/268 ,  G06F9/3861

摘要： A state recovery and restart method that simplifies assist handling. The recovery and restart method also handles micro-branch mispredictions. An assist sequence is executed in microcode to assist an error-causing macroinstruction. If data is required from an error-causing macroinstruction, it is fetched, decoded, and macro-alias registers are restored with macro-alias data. To recover the state of the micro-alias registers, micro-alias data from a micro-operation of the flow may be loaded into the micro-alias register. Subsequently, control returns to the Micro-operation Sequence (MS) unit to issue further error correction Control micro-operations (Cuops). In order to simplify restart, the Cuops originating from the error-causing macroinstruction supplied by the translate programmable logic arrays (XLAT PLAs) are loaded into the Cuop registers, with their valid bits unasserted. If microcode requests a restart beginning at one of the Cuops stored in the Cuop register, then the bits for that Cuop and subsequent Cuops are marked valid. Thus, the instruction can be restarted anywhere within the microcode sequence.

摘要翻译： 一种简化辅助处理的状态恢复和重启方法。 恢复和重新启动方法也处理微分支错误预测。 在微代码中执行辅助序列以辅助引起错误的宏指令。 如果需要来自导致错误的宏指令的数据，则会获取，解码和使用宏别名数据恢复宏别名寄存器。 为了恢复微别名寄存器的状态，来自流程的微操作的微别名数据可以被加载到微别名寄存器中。 随后，控制返回到微操作序列（MS）单元以发出进一步的纠错控制微操作（Cuops）。 为了简化重新启动，由翻译可编程逻辑阵列（XLAT PLA）提供的引起误差的宏指令产生的钳位被加载到Cuop寄存器中，其有效位被置为无效。 如果微码请求从Cuop寄存器中存储的一个Cuops开始重新启动，那么该Cuop和后续Cuops的位将被标记为有效。 因此，可以在微代码序列内的任何地方重新启动指令。

公开(公告)号：US06807592B2

公开(公告)日：2004-10-19

申请号：US09925691

申请日：2001-08-10

申请人： Gurbir Singh ,  Robert J. Greiner ,  Stephen S. Pawlowski ,  David L. Hill ,  Donald D. Parker

发明人： Gurbir Singh ,  Robert J. Greiner ,  Stephen S. Pawlowski ,  David L. Hill ,  Donald D. Parker

IPC分类号： G06F1300

CPC分类号： G06F13/4217

摘要： A bidirectional multidrop processor bus is connected to a plurality of bus agents. Bus throughput can be increased by operating the bus in a multi pumped signaling mode in which multiple information elements are driven onto a bus by a driving agent at a rate that is a multiple of the frequency of the bus clock. The driving agent also activates a strobe to identify sampling points for the information elements. Information elements for a request can be driven, for example, using a double pumped signaling mode in which two information elements are driven during one bus clock cycle. Data elements for a data line transfer can be driven, for example, using a quad pumped signaling mode in which four data elements are driven during one bus clock cycle. Multiple strobe signals can be temporarily activated in an offset or staggered arrangement to reduce the frequency of the strobe signals. Sampling symmetry can be improved by using only one type of edge (e.g., either the rising edges or the falling edges) of the strobe signals to identify the sampling points.

摘要翻译： 双向多点处理器总线连接到多个总线代理。 可以通过以多抽头信令模式操作总线来增加总线吞吐量，其中多个信息元素以驱动代理以总线时钟频率的倍数的速率被驱动到总线上。 驱动代理还激活选通以识别信息元素的采样点。 可以例如使用双泵浦信号模式来驱动请求的信息元素，其中在一个总线时钟周期期间驱动两个信息元素。 数据线传输的数据元素例如可以使用四泵浦信号模式来驱动，其中四个数据元件在一个总线时钟周期内被驱动。 可以以偏移或交错布置临时地激活多个选通信号，以减少选通信号的频率。 可以通过仅使用选通信号的一种类型的边缘（例如，上升沿或下降沿）来提高采样对称性，以识别采样点。

公开(公告)号：US06804735B2

公开(公告)日：2004-10-12

申请号：US09784244

申请日：2001-02-14

申请人： Gurbir Singh ,  Robert J. Greiner ,  Stephen S. Pawlowski ,  David L. Hill ,  Donald D. Parker

发明人： Gurbir Singh ,  Robert J. Greiner ,  Stephen S. Pawlowski ,  David L. Hill ,  Donald D. Parker

IPC分类号： G06F1300

CPC分类号： G06F13/4217

摘要： A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a target ready interface, a set of response interfaces for a set of response signals, and a data bus busy interface, and a bus clock interface for a bus clock signal. The bus agent of this embodiment also includes bus controller logic to track a plurality of transactions comprising a transaction N-1 and a transaction N, the bus controller being capable of asserting the target ready signal for transaction N if the bus agent is asserting the data busy signal for the transaction N-1 and deasserts the data busy signal.

摘要翻译： 可用于增强的高流水线总线架构中的总线代理。 在一个实施例中，总线代理包括目标就绪接口，用于一组响应信号的一组响应接口和数据总线忙接口以及用于总线时钟信号的总线时钟接口。 该实施例的总线代理还包括总线控制器逻辑以跟踪包括事务N-1和事务N的多个事务，总线控制器能够为事务N断言目标就绪信号，如果总线代理正在断言数据 忙信号用于事务N-1，并取消对数据忙信号的否定。