公开(公告)号：US20220138441A1

公开(公告)日：2022-05-05

申请号：US17434921

申请日：2019-03-01

Applicant: TDK CORPORATION

Inventor： Tatsuo SHIBATA ,  Yukio TERASAKI

IPC: G06G7/32 ,  G06N3/063

Abstract: A multiply and accumulate calculation device including a variable resistor array unit having a plurality of variable resistance elements, a reference array unit having a reference resistance element having a fixed resistance value, a signal input unit that generates an input signal from input data, and inputs the input signal to the variable and reference resistance elements, a first detection unit that detects a current flowing through the variable resistor array unit, based on the input signal applied to the variable resistance elements, a second detection unit that detects a current flowing through the reference array unit, based on the input signal applied to the reference resistance element, and a correction calculation unit that performs a predetermined calculation on the output from the first detection unit, based on the output from the second.

公开(公告)号：US20230033927A1

公开(公告)日：2023-02-02

申请号：US17789998

申请日：2020-02-27

Applicant: TDK CORPORATION

Inventor： Yukio TERASAKI

IPC: G06N3/063

Abstract: A reservoir element includes a plurality of units. Each of units constituting the plurality of units is connected to at least one or more different units. Each of the plurality of units includes an input terminal to which a first signal is input, a resistor which is connected to the input terminal, a capacitor which is connected to an opposite side of the resistor to the input terminal and is provided between the resistor and a reference potential, a switching element which is connected to the capacitor, and an output terminal which is connected to the switching element. At least one of the plurality of units differs from other units in an RC time constant.

公开(公告)号：US20220092396A1

公开(公告)日：2022-03-24

申请号：US17420915

申请日：2019-01-09

Applicant: TDK CORPORATION

Inventor： Kuniyasu ITO ,  Tatsuo SHIBATA ,  Yukio TERASAKI

IPC: G06N3/063 ,  G06F7/523 ,  G06F7/50

Abstract: A product-sum operation device including: product operation units generating output signals by multiplying input signals corresponding to input values; a current detection unit executing a current detecting process in which a current output from the product operation units with a predetermined time delay from input of the input signal and a current output from the product operation units at an interval thereafter are detected in a time span from a first transient response to before occurrence of a second transient response, the first transient response due to charging to a parasitic capacitance of the product operation units by input of the input signal and the second transient response being due to discharging from the parasitic capacitance of the product operation units by input of the input signal; and a sum operation unit calculating a value relating to a total sum of the output signals based on currents detected.

公开(公告)号：US20240020520A1

公开(公告)日：2024-01-18

申请号：US17865966

申请日：2022-07-15

Applicant: TDK CORPORATION

Inventor： Shogo YAMADA ,  Keita SUDA ,  Yukio TERASAKI ,  Tomoyuki SASAKI

IPC: G06N3/063 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

CPC classification number: G06N3/063 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

Abstract: A memristor includes a first variable conductance element and a second variable conductance element. A minimum value of conductance of the second variable conductance element during reading is larger than a maximum value of conductance of the first variable conductance element during reading. In the memristor, a first read path when the conductance of the first variable conductance element is read merges with a second read path when the conductance of the second variable conductance element is read.

公开(公告)号：US20230229900A1

公开(公告)日：2023-07-20

申请号：US18125997

申请日：2023-03-24

Applicant: TDK CORPORATION

Inventor： Yukio TERASAKI

IPC: G06N3/063 ,  G06N3/04

CPC classification number: G06N3/063 ,  G06N3/04

Abstract: A controller is a controller of an array including a neuromorphic element that multiplies a weight based on a value of a variable characteristic by a signal, and includes a control unit that controls the characteristic of the neuromorphic element by using a discretization step size obtained so that a predetermined condition for reducing an error or a predetermined condition for improving accuracy is satisfied on the basis of a case where a true value of the weight obtained with a higher accuracy than a resolution of the characteristic of the neuromorphic element is used and a case where a discretization step size which is set for the characteristic of the neuromorphic element is used.

公开(公告)号：US20200272891A1

公开(公告)日：2020-08-27

申请号：US16643660

申请日：2018-02-19

Applicant: TDK CORPORATION

Inventor： Yukio TERASAKI

IPC: G06N3/063 ,  G06N3/08 ,  G06F7/523 ,  G06F7/544

Abstract: A controller is a controller of an array including a neuromorphic element that multiplies a weight based on a value of a variable characteristic by a signal, and includes a control unit that controls the characteristic of the neuromorphic element by using a discretization step size obtained so that a predetermined condition for reducing an error or a predetermined condition for improving accuracy is satisfied on the basis of a case where a true value of the weight obtained with a higher accuracy than a resolution of the characteristic of the neuromorphic element is used and a case where a discretization step size which is set for the characteristic of the neuromorphic element is used.

公开(公告)号：US20240169181A1

公开(公告)日：2024-05-23

申请号：US18239332

申请日：2023-08-29

Applicant: TDK CORPORATION

Inventor： Yukio TERASAKI

IPC: G06N3/044 ,  G06N3/063 ,  G06N5/04 ,  H03M1/12

CPC classification number: G06N3/044 ,  G06N3/063 ,  G06N5/04 ,  H03M1/1245

Abstract: A signal processor includes an input unit, an analog-digital converter, a control circuit, and a reservoir unit. The input unit receives a first analog signal. The analog-digital converter converts the first analog signal to a first digital signal. The control circuit detects the first analog signal or the first digital signal and outputs a control signal for extracting a part of the first analog signal or the first digital signal. The reservoir unit receives at least a part of the first digital signal and operates in synchronization with at least a part of the control signal.

公开(公告)号：US20220309339A1

公开(公告)日：2022-09-29

申请号：US17496934

申请日：2021-10-08

Applicant: TDK CORPORATION

Inventor： Yukio TERASAKI ,  Kazuki NAKADA

IPC: G06N3/08 ,  G06N3/063 ,  G06N3/04

Abstract: An information processing device includes a reservoir layer, and a read-out layer. The reservoir layer includes a plurality of nodes that generate a feature space including information of an input signal input to the reservoir layer, the read-out layer performs an operation of applying a connection weight to each of signals sent from the reservoir layer, and the number of signals sent to the read-out layer from the reservoir layer is smaller than the number of the plurality of nodes.

公开(公告)号：US20220261559A1

公开(公告)日：2022-08-18

申请号：US17627027

申请日：2020-02-27

Applicant: TDK CORPORATION

Inventor： Tatsuo SHIBATA ,  Yukio TERASAKI

IPC: G06G7/60 ,  G06N3/063 ,  G06F7/544

Abstract: An arithmetic circuit includes a variable resistance element having three terminals of a first terminal, a second terminal, and a third terminal and configured such that the resistance value is variable, an input line connected to the first terminal, a capacitor connected to the second terminal and provided between the second terminal and the reference potential, a first switching element connected to the third terminal, a wiring connected to the third terminal through the first switching element, a second switching element connected to a first end of the wiring, and a third switching element connected to a second end of the wiring.

公开(公告)号：US20220130900A1

公开(公告)日：2022-04-28

申请号：US17271875

申请日：2020-02-27

Applicant: TDK CORPORATION

Inventor： Yukio TERASAKI

IPC: H01L27/22 ,  G06N3/063 ,  H01L43/08

Abstract: An arithmetic operation circuit including: a variable resistance element that includes three terminals that are a first terminal, a second terminal, and a third terminal and is configured to be able to change a resistance value; a first electrode connected to the first terminal; a second electrode; a third electrode; a first switching element connected between the second electrode and the second terminal; a second switching element connected between the third electrode and the third terminal; and a capacitor connected between a transmission line connecting the second terminal and the first switching element and the ground.