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公开(公告)号：US11757351B2
公开(公告)日：2023-09-12
申请号：US17390539
申请日：2021-07-30
Applicant: Texas Instruments Incorporated
Inventor： Ammineni Balaji , Preetam Charan Anand Tadeparthy , Naman Bafna , Sreelakshmi Suresh , Cheng Wei Chen
Abstract: Described embodiments include a voltage regulator circuit comprising a first comparator having a first comparator input coupled to a waveform input source, a second comparator input coupled to an output voltage terminal and a first comparator output. There is a second comparator having third and fourth comparator inputs and a second comparator output, the third comparator input coupled to a voltage source configured to provide a voltage representing a current limit, and the fourth comparator input coupled to the output voltage terminal. There is also a state machine having a first state machine input coupled to the first comparator output, a second state machine input coupled to the second comparator output and a state machine output, wherein a state of the state machine is determined by the first and second comparator outputs, and the state machine output provides a PWM signal responsive to the state of the state machine.
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公开(公告)号：US12015345B2
公开(公告)日：2024-06-18
申请号：US18229755
申请日：2023-08-03
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Naman Bafna , Preetam Charan Anand Tadeparthy , Ammineni Balaji , Sreelakshmi Suresh , Mayank Jain
CPC classification number: H02M3/157 , H02M1/0009 , H02M1/0845
Abstract: In an example, a method includes storing a pending PWM pulse for a switching voltage regulator. The method also includes determining a switching voltage regulator is operating in a current limit mode, where an inductor current is above a current limit threshold. The method includes providing a predetermined number of PWM pulses in the current limit mode. The method also includes, responsive to providing the predetermined number of PWM pulses, ceasing storage of pending PWM pulses for the switching voltage regulator.
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Patent Agency Ranking
公开(公告)号：US20230035151A1
公开(公告)日：2023-02-02
申请号：US17390539
申请日：2021-07-30
Applicant: Texas Instruments Incorporated
Inventor： Ammineni Balaji , Preetam Charan Anand Tadeparthy , Naman Bafna , Sreelakshmi Suresh , Cheng Wei Chen
Abstract: Described embodiments include a voltage regulator circuit comprising a first comparator having a first comparator input coupled to a waveform input source, a second comparator input coupled to an output voltage terminal and a first comparator output. There is a second comparator having third and fourth comparator inputs and a second comparator output, the third comparator input coupled to a voltage source configured to provide a voltage representing a current limit, and the fourth comparator input coupled to the output voltage terminal. There is also a state machine having a first state machine input coupled to the first comparator output, a second state machine input coupled to the second comparator output and a state machine output, wherein a state of the state machine is determined by the first and second comparator outputs, and the state machine output provides a PWM signal responsive to the state of the state machine.
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公开(公告)号：US11757358B2
公开(公告)日：2023-09-12
申请号：US17490671
申请日：2021-09-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Naman Bafna , Preetam Charan Anand Tadeparthy , Ammineni Balaji , Sreelakshmi Suresh , Mayank Jain
CPC classification number: H02M3/157 , H02M1/0009 , H02M1/0845
Abstract: In an example, a method includes storing a pending PWM pulse for a switching voltage regulator. The method also includes determining a switching voltage regulator is operating in a current limit mode, where an inductor current is above a current limit threshold. The method includes providing a predetermined number of PWM pulses in the current limit mode. The method also includes, responsive to providing the predetermined number of PWM pulses, ceasing storage of pending PWM pulses for the switching voltage regulator.
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公开(公告)号：US11711016B2
公开(公告)日：2023-07-25
申请号：US17489782
申请日：2021-09-30
Applicant: Texas Instruments Incorporated
Inventor： Naman Bafna , Preetam Charan Anand Tadeparthy , Ammineni Balaji , Sreelakshmi Suresh
CPC classification number: H02M3/158 , H02M1/0025
Abstract: In described examples of a system having a proportional-integral control module, an error signal is produced that is indicative of a difference between a reference signal and an output signal. An integral control signal is produced by integrating the error signal using an integrator time constant value. During a steady state condition, a first integrator time constant value is used. When an undershoot in the output signal is detected, the integrator time constant value is increased to a second time constant value that is larger than the first integrator time constant value during the undershoot condition. The integrator time constant value is reduced to a third integrator time constant value that is less than the first integrator time constant value during a period following the undershoot condition.
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公开(公告)号：US11811326B2
公开(公告)日：2023-11-07
申请号：US17682747
申请日：2022-02-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Naman Bafna , Cheng Wei Chen , Preetam Charan Anand Tadeparthy , Sreelakshmi Suresh , Ammineni Balaji
CPC classification number: H02M3/1586 , H02M1/0003 , H02M3/1584 , H02M3/1566
Abstract: An example circuit includes a loop controller having current phase inputs, a feedback input, a control loop output and a transient event output. The feedback input is adapted to be coupled to an output terminal of a multi-phase power stage. A PWM circuit has a blanking input, a control input and a PWM output, the control input coupled to the control loop output. A phase management circuit has a transient detect input, a PWM input, a blanking output and phase outputs. The transient detect input is coupled to the transient event output. The PWM input is coupled to the PWM output and the blanking output is coupled to the blanking input. Each of the phase outputs is adapted to be coupled to a respective phase of the multi-phase power stage. The phase management circuit is configured to provide a blanking control signal representative of a variable blanking time.
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公开(公告)号：US20230079601A1
公开(公告)日：2023-03-16
申请号：US17489782
申请日：2021-09-30
Applicant: Texas Instruments Incorporated
Inventor： Naman Bafna , Preetam Charan Anand Tadeparthy , Ammineni Balaji , Sreelakshmi Suresh
Abstract: In described examples of a system having a proportional-integral control module, an error signal is produced that is indicative of a difference between a reference signal and an output signal. An integral control signal is produced by integrating the error signal using an integrator time constant value. During a steady state condition, a first integrator time constant value is used. When an undershoot in the output signal is detected, the integrator time constant value is increased to a second time constant value that is larger than the first integrator time constant value during the undershoot condition. The integrator time constant value is reduced to a third integrator time constant value that is less than the first integrator time constant value during a period following the undershoot condition.
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