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    REDUCING TRANSISTOR BREAKDOWN IN A POWER FET CURRENT SENSE STACK
    1.
    发明申请
    REDUCING TRANSISTOR BREAKDOWN IN A POWER FET CURRENT SENSE STACK 有权

    公开(公告)号：US20230006060A1

    公开(公告)日：2023-01-05

    申请号：US17682370

    申请日：2022-02-28

    Applicant: Texas Instruments Incorporated

    Inventor： Henry Litzmann Edwards ,  Narayana Sateesh Pillai ,  Gangqiang Zhang ,  Angelo William Pereira

    IPC: H01L29/78 ,  H01L29/66

    Abstract: An integrated circuit includes a first field effect transistor (FET) and a second FET formed in or over a semiconductor substrate and configured to selectively conduct a current between a first circuit node and a second circuit node. The first FET has a first source, a first drain and a first buried layer all having a first conductivity type, and a first gate between the first source and the first drain. The second FET has a second source, a second drain and a second buried layer all having the first conductivity type, and a second gate between the second source and the second drain. A first potential between the first source and the first buried layer is configurable independently from a second potential between the second source and the second buried layer.

    Multi-mode voltage regulator
    2.
    发明授权
    Multi-mode voltage regulator 有权

    公开(公告)号：US10802517B1

    公开(公告)日：2020-10-13

    申请号：US16455056

    申请日：2019-06-27

    Applicant: Texas Instruments Incorporated

    Inventor： Rida Shawky Assaad ,  Angelo William Pereira ,  Terry Lee Mayhugh, Jr.

    IPC: G05F1/46 ,  G05F1/56

    Abstract: A voltage regulator circuit includes a bias circuit having an input and an output. The input of the bias circuit is coupled to an input voltage supply rail. A Zener diode has a cathode coupled to the output of the bias circuit. A resistor network is coupled to the output of the bias circuit. The resistor network includes a first circuit path, which includes a first resistor, connected in parallel with the Zener diode and a second circuit path, which includes a second resistor, coupled between the output of the bias circuit and a node. A current control circuit is coupled to the bias circuit and the resistor network. An output stage has an input and an output. The input of the output stage is coupled to the node.

    High-speed short-to-ground protection circuit for pass field-effect transistor (FET)
    4.
    发明授权
    High-speed short-to-ground protection circuit for pass field-effect transistor (FET) 有权

    公开(公告)号：US11217992B2

    公开(公告)日：2022-01-04

    申请号：US16843324

    申请日：2020-04-08

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Kae Ann Wong ,  Siang Tong Tan ,  Luis Ariel Malave-Perez ,  Mikko Topi Loikkanen ,  Mitsuyori Saito ,  Angelo William Pereira

    IPC: H02H9/04 ,  H02H1/00

    Abstract: A system includes a power supply source and a power control circuit coupled to the power supply source, in which the power control circuit includes a pass field-effect transistor (FET). The system also includes a short-to-ground protection circuit coupled to an output of the pass FET. The short-to-ground protection circuit includes a sense circuit configured to detect when a magnitude and a change rate of a voltage drop at the output of the pass FET is greater than respective thresholds. The short-to-ground protection circuit also includes a control node at the output of the sense circuit. The sense circuit is configured to induce a control current at the control node in response to the magnitude and the change rate of a voltage drop at the output of the pass FET being greater than respective thresholds. The control current is used to turn off the pass FET.

    Transient-insensitive level shifter
    9.
    发明授权
    Transient-insensitive level shifter 有权

    公开(公告)号：US10916653B2

    公开(公告)日：2021-02-09

    申请号：US16160470

    申请日：2018-10-15

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Rida Shawky Assaad ,  Angelo William Pereira

    IPC: H01L29/78 ,  H03K19/0185

    Abstract: In a described example, an apparatus includes at least one latch coupled to a first positive supply voltage and to a first negative supply voltage, the latch having a first inverter and a second inverter coupled to one another back to back, to output a first voltage corresponding to a first latch state and a second voltage corresponding to a second latch state responsive to a first set signal and a first reset signal. An isolation circuit is coupled to a second positive supply voltage and to a second negative supply voltage and is coupled to receive a second set signal, and a second reset signal. The second positive supply voltage is independent of the first positive supply voltage. The isolation circuit outputs the first set signal and the first reset signal and includes less than two pairs of drain extended metal oxide semiconductor (DEMOS) transistors.

    TRANSIENT-INSENSITIVE LEVEL SHIFTER
    10.
    发明申请
    TRANSIENT-INSENSITIVE LEVEL SHIFTER 审中-公开

    公开(公告)号：US20190207026A1

    公开(公告)日：2019-07-04

    申请号：US16160470

    申请日：2018-10-15

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Rida Shawky Assaad ,  Angelo William Pereira

    IPC: H01L29/78 ,  H03K19/0185

    CPC classification number: H01L29/7835 ,  H03K19/018507

    Abstract: In a described example, an apparatus includes at least one latch coupled to a first positive supply voltage and to a first negative supply voltage, the latch having a first inverter and a second inverter coupled to one another back to back, to output a first voltage corresponding to a first latch state and a second voltage corresponding to a second latch state responsive to a first set signal and a first reset signal. An isolation circuit is coupled to a second positive supply voltage and to a second negative supply voltage and is coupled to receive a second set signal, and a second reset signal. The second positive supply voltage is independent of the first positive supply voltage. The isolation circuit outputs the first set signal and the first reset signal and includes less than two pairs of drain extended metal oxide semiconductor (DEMOS) transistors.

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