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公开(公告)号：US20190146536A1
公开(公告)日：2019-05-16
申请号：US16247198
申请日：2019-01-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sujan Kundapur Manohar , Angelo William Pereira , Ashish Khandelwal
Abstract: A voltage regulator (such as a low drop-out regulator) includes a pass transistor coupled to an input voltage node and an output voltage node. The voltage regulator also includes a drive transistor coupled to a control input of the pass transistor and a first resistor coupled between a source and a back gate of the drive transistor. The voltage regulator also includes a complementary to absolute temperature (CTAT) current generator circuit coupled to the resistor and configured to generate a CTAT current to bias the first resistor.
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公开(公告)号：US11430722B2
公开(公告)日：2022-08-30
申请号：US15951003
申请日：2018-04-11
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jeffrey Morroni , Rajeev Dinkar Joshi , Sreenivasan K. Koduri , Sujan Kundapur Manohar , Yogesh K. Ramadass , Anindya Poddar
IPC: H01L23/00 , H01L23/495 , H01L23/498 , H01L21/48 , H01L23/50
Abstract: A semiconductor package includes a leadframe, a semiconductor die attached to the leadframe, and a passive component electrically connected to the semiconductor die through the leadframe. The leadframe includes a cavity in a side of the leadframe opposite the semiconductor die, and at least a portion of the passive component resides within the cavity in a stacked arrangement.
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公开(公告)号：US20200280309A1
公开(公告)日：2020-09-03
申请号：US16877128
申请日：2020-05-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sujan Kundapur Manohar , Michael James Mills , Justin Patrick Vogt
IPC: H03K17/14 , H03K17/06 , G06F13/42 , G05F3/24 , H03K17/687
Abstract: A power supply system for USB Power Delivery includes a current source drive circuit to control a power FET to regulate the supply of power along a power path. The current source drive circuit includes a cascode current source and a cascode protection circuit formed by a source follower and a feedback voltage divider. The source follower can be a transistor with its gate connected to a cascode node between upper- and lower-stage transistors of the cascode current source. The divider node of the voltage divider is connected to the gate of the lower-stage transistor. The current source drive circuit can operate within the gate-source voltage specifications of 30-volt DEPMOS devices, and can provide high output impedance to the gate of power FET and a current limit circuit during current limiting operation, without requiring an extra high-voltage mask during fabrication.
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公开(公告)号：US11575372B2
公开(公告)日：2023-02-07
申请号：US16877128
申请日：2020-05-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sujan Kundapur Manohar , Michael James Mills , Justin Patrick Vogt
Abstract: A power supply system for USB Power Delivery includes a current source drive circuit to control a power FET to regulate the supply of power along a power path. The current source drive circuit includes a cascode current source and a cascode protection circuit formed by a source follower and a feedback voltage divider. The source follower can be a transistor with its gate connected to a cascode node between upper- and lower-stage transistors of the cascode current source. The divider node of the voltage divider is connected to the gate of the lower-stage transistor. The current source drive circuit can operate within the gate-source voltage specifications of 30-volt DEPMOS devices, and can provide high output impedance to the gate of power FET and a current limit circuit during current limiting operation, without requiring an extra high-voltage mask during fabrication.
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5.发明授权公开(公告)号：US10782727B2
公开(公告)日：2020-09-22
申请号：US16194784
申请日：2018-11-19
Applicant: Texas Instruments Incorporated
Inventor： Angelo William Pereira , Pinar Korkmaz , Sujan Kundapur Manohar
Abstract: Integrated circuits having self-calibrating oscillators, and methods of operating the same are disclosed. A disclosed example integrated circuit includes a clock generator, a comparator having a first input connected to an output of the clock generator and a second input connected to a reference voltage, a calibration done detector having an input connected to an output of the comparator and an output communicatively coupled to a calibration code register.
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Patent Agency Ranking
公开(公告)号：US10180694B2
公开(公告)日：2019-01-15
申请号：US15655373
申请日：2017-07-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sujan Kundapur Manohar , Angelo William Pereira , Ashish Khandelwal
Abstract: A voltage regulator (e.g., a low drop-out regulator) includes a pass transistor coupled to an input voltage node and an output voltage node. The voltage regulator also includes a drive transistor coupled to a control input of the pass transistor and a first resistor coupled between a source and a back gate of the drive transistor. The voltage regulator also includes a complementary to absolute temperature (CTAT) current generator circuit coupled to the resistor and configured to generate a CTAT current to bias the first resistor.
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公开(公告)号：US10979037B2
公开(公告)日：2021-04-13
申请号：US16167151
申请日：2018-10-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sujan Kundapur Manohar , Roland Karl Son , Juergen Luebbe , Eddie W. Yu
IPC: H02H3/087 , H03K5/08 , H03K17/0812 , H02H3/18 , H02H3/08 , H03K17/082 , H02H9/02 , H02H3/44
Abstract: In described examples, a power interface subsystem includes power transistors, each having: a conduction path coupled between a battery terminal and an accessory terminal; and a control terminal. A differential amplifier has: a first input coupled to the battery terminal; a second input coupled to the accessory terminal; and an output node. An offset voltage source is coupled to cause an offset of a selected polarity at one of the inputs to the differential amplifier. The offset has a first polarity in a first operating mode and a second polarity in a second operating mode. Gate control circuitry is coupled to apply a control level at the control terminal(s) of selected one(s) of the power transistors responsive to a voltage at the output node, and to apply an off-state control level to the control terminal(s) of unselected one(s) of the power transistors.
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公开(公告)号：US10673423B2
公开(公告)日：2020-06-02
申请号：US15234722
申请日：2016-08-11
Applicant: Texas Instruments Incorporated
IPC: G05F1/10 , H03K5/08 , H03K17/042
Abstract: In described examples, in response to a voltage at an external power terminal falling below a safe limit: a charge pump is operated at a first frequency to produce a voltage at a charge pump node; and a first controlled current is coupled from the charge pump node to a control terminal of a power switch transistor. The power switch transistor has a conduction path coupled between the external power terminal and an internal power terminal at which an internal power source is connected. In response to the voltage at the external power terminal reaching a selected level: the charge pump is operated at a second frequency, lower than the first frequency; and a second controlled current, lower than the first controlled current, is coupled from the charge pump node to the control terminal of the power switch transistor.
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公开(公告)号：US10659033B2
公开(公告)日：2020-05-19
申请号：US15802787
申请日：2017-11-03
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sujan Kundapur Manohar , Michael James Mills , Justin Patrick Vogt
Abstract: A power supply system for USB Power Delivery includes a current source drive circuit to control a power FET to regulate the supply of power along a power path. The current source drive circuit includes a cascode current source and a cascode protection circuit formed by a source follower and a feedback voltage divider. The source follower can be a transistor with its gate connected to a cascode node between upper- and lower-stage transistors of the cascode current source. The divider node of the voltage divider is connected to the gate of the lower-stage transistor. The current source drive circuit can operate within the gate-source voltage specifications of 30-volt DEPMOS devices, and can provide high output impedance to the gate of power FET and a current limit circuit during current limiting operation, without requiring an extra high-voltage mask during fabrication.
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公开(公告)号：US20190058463A1
公开(公告)日：2019-02-21
申请号：US16167151
申请日：2018-10-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sujan Kundapur Manohar , Roland Karl Son , Juergen Luebbe , Eddie W. Yu
IPC: H03K5/08 , H03K17/0812 , H02H3/18 , H02H3/087 , H02H3/08 , H03K17/082 , H02H9/02
Abstract: In described examples, a power interface subsystem includes power transistors, each having: a conduction path coupled between a battery terminal and an accessory terminal; and a control terminal. A differential amplifier has: a first input coupled to the battery terminal; a second input coupled to the accessory terminal; and an output node. An offset voltage source is coupled to cause an offset of a selected polarity at one of the inputs to the differential amplifier. The offset has a first polarity in a first operating mode and a second polarity in a second operating mode. Gate control circuitry is coupled to apply a control level at the control terminal(s) of selected one(s) of the power transistors responsive to a voltage at the output node, and to apply an off-state control level to the control terminal(s) of unselected one(s) of the power transistors.
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