中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

7 records (took 0.015 seconds)

    TRANSDUCER INTERFACE PAIR IMPEDANCE MEASUREMENT
    2.
    发明申请
    TRANSDUCER INTERFACE PAIR IMPEDANCE MEASUREMENT 审中-公开

    公开(公告)号：US20190039091A1

    公开(公告)日：2019-02-07

    申请号：US16053662

    申请日：2018-08-02

    Applicant: Texas Instruments Incorporated

    Inventor： Krishnaswamy Nagaraj ,  Asif Qaiyum ,  Baher S. Haroun

    IPC: B06B1/02 ,  H03K17/687 ,  G01F1/66

    Abstract: In described examples, a first and second driver each include a first-rail output transistor including a first terminal coupled to a first power rail and a second-rail output transistor including a first terminal coupled to a second power rail. The first-rail output transistor of each of the first and second drivers includes a second terminal coupled to a second terminal of the second-rail output transistor of an output node of each respective first and second driver. A resistive load includes a first terminal coupled to the first-driver output node and includes a second terminal coupled to the second-driver output node. A sampling circuit generates an indication of an impedance of at least one of the output transistors of the first and second drivers.

    Digital LDO passgate rotation
    3.
    发明授权
    Digital LDO passgate rotation 有权

    公开(公告)号：US12079019B2

    公开(公告)日：2024-09-03

    申请号：US17323924

    申请日：2021-05-18

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Johannes Gerber ,  Asif Qaiyum ,  Fraj Gharib ,  Christian Josef Sichert ,  Ruediger Kuhn ,  Frank Dornseifer ,  Bernhard Wolfgang Ruck

    IPC: G05F1/575

    CPC classification number: G05F1/575

    Abstract: A system includes a digital controller in a voltage regulator. The system also includes a passgate array including two or more passgate transistors, where the passgate array is configured to provide a load current to a load, and where the digital controller is configured to activate and deactivate each passgate transistor in the passgate array. The system also includes a feedback loop configured to provide an error signal to the digital controller, the error signal based on a difference between an output voltage of the voltage regulator and a programmed voltage for the voltage regulator. The digital controller is configured to activate or deactivate a passgate transistor based at least in part on the error signal. The digital controller is also configured to activate at least one passgate transistor and deactivate at least one passgate transistor responsive to a clock cycle.

    Constant ripple algorithm in DCM for buck converter
    4.
    发明授权
    Constant ripple algorithm in DCM for buck converter 有权

    公开(公告)号：US12301096B2

    公开(公告)日：2025-05-13

    申请号：US18439923

    申请日：2024-02-13

    Applicant: Texas Instruments Incorporated

    Inventor： Asif Qaiyum ,  Ruediger Kuhn ,  Martin Schneider

    IPC: H02M1/14 ,  H02M1/00 ,  H02M3/158

    Abstract: A ripple voltage detector circuit comprises a pulse generator, a direct current-to-direct current (DC-DC) converter coupled to the pulse generator, and a first control loop coupled to the pulse generator and the DC-DC converter. The first control loop is configured to measure an output voltage of the DC-DC converter, determine an output ripple voltage of the output voltage, determine a ripple coefficient based on the output ripple voltage, determine a reference peak inductor current based on the ripple coefficient, and determine a peak value of an inductor current during a switching cycle, and transition a switching state of the DC-DC converter based on the reference peak inductor current and the peak value of the inductor current.

    Transducer interface pair impedance measurement
    7.
    发明授权
    Transducer interface pair impedance measurement 有权

    公开(公告)号：US11247232B2

    公开(公告)日：2022-02-15

    申请号：US16053662

    申请日：2018-08-02

    Applicant: Texas Instruments Incorporated

    Inventor： Krishnaswamy Nagaraj ,  Asif Qaiyum ,  Baher S. Haroun

    IPC: B06B1/02 ,  G01F1/66 ,  H03K17/687

    Abstract: In described examples, a first and second driver each include a first-rail output transistor including a first terminal coupled to a first power rail and a second-rail output transistor including a first terminal coupled to a second power rail. The first-rail output transistor of each of the first and second drivers includes a second terminal coupled to a second terminal of the second-rail output transistor of an output node of each respective first and second driver. A resistive load includes a first terminal coupled to the first-driver output node and includes a second terminal coupled to the second-driver output node. A sampling circuit generates an indication of an impedance of at least one of the output transistors of the first and second drivers.

Patent Agency Ranking