公开(公告)号：US12094524B2

公开(公告)日：2024-09-17

申请号：US17162694

申请日：2021-01-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Avishek Biswas ,  Mahesh Madhukar Mehendale ,  Hetul Sanghvi

IPC: G11C11/4094 ,  G06G7/16 ,  G06N3/065 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/4097 ,  G11C11/4099 ,  G11C11/54

CPC classification number: G11C11/4094 ,  G06G7/16 ,  G06N3/065 ,  G11C5/06 ,  G11C7/1006 ,  G11C11/4074 ,  G11C11/4097 ,  G11C11/4099 ,  G11C11/54

Abstract: A device includes a bit cell having first and second terminals, a first bit line coupled to the first terminal, a second bit line coupled to the second terminal, a first capacitor, a second capacitor, and a multiply and average (MAV) circuit coupled to the first capacitor, to the second capacitor, to the first bit line, and to the second bit line. The MAV circuit includes a first transistor coupled to the first capacitor and to a ground terminal and a second transistor coupled to the second capacitor and to the ground terminal. The first transistor has a first transistor control terminal selectively coupled to the first bit line and the second transistor has a second transistor control terminal selectively coupled to the second bit line.

公开(公告)号：US11551745B2

公开(公告)日：2023-01-10

申请号：US17162842

申请日：2021-01-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Avishek Biswas ,  Mahesh Madhukar Mehendale

IPC: G11C5/06 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/4074 ,  G11C11/4099 ,  G06F7/52 ,  G11C11/54 ,  G11C7/10 ,  G06N3/063 ,  G06N3/04 ,  G11C7/16 ,  G11C11/412

Abstract: A device includes a comparator to provide an indication of a difference between Vp on a first terminal coupled to a top plate of each of a first group of differential capacitors, and Vn on a second terminal coupled to a top plate of each of a second group of differential capacitors. The device includes a control circuit coupled to the comparator. The control circuit is to receive a first indication of a difference between Vp and Vn; responsive to the first indication, cause a first driver to provide a reference voltage to bottom plates of one of the first and second groups, and cause a second driver to provide a ground voltage to bottom plates of the other of the first and second groups; receive a second indication of a difference between Vp and Vn; and provide a digital value responsive to the first indication and the second indication.

公开(公告)号：US20250029652A1

公开(公告)日：2025-01-23

申请号：US18883541

申请日：2024-09-12

Applicant: Texas Instruments Incorporated

Inventor： Avishek Biswas ,  Mahesh Madhukar Mehendale ,  Hetul Sanghvi

IPC: G11C11/4094 ,  G06G7/16 ,  G06N3/065 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/4097 ,  G11C11/4099 ,  G11C11/54

Abstract: A device includes a first bit cell, a second bit cell, and a multiply and average (MAV) circuit. The MAV circuit includes a first selection circuit and a second selection circuit. The first selection circuit has a first selection input and coupled to first and second capacitor terminals, and the first selection circuit is configured to, responsive to a state of the first selection input, set respective states of the first and second capacitor terminals based on a state of the first bit cell. The second selection circuit has a second selection input and is coupled to the first and second capacitor terminals. The second selection circuit is configured to, responsive to a state of the second selection input, set the respective states of the first and second capacitor terminals based on a state of the second bit cell.

公开(公告)号：US20240364354A1

公开(公告)日：2024-10-31

申请号：US18343289

申请日：2023-06-28

Applicant: Texas Instruments Incorporated

Inventor： Avishek Biswas ,  Hetul Sanghvi

IPC: H03M1/10

CPC classification number: H03M1/1014

Abstract: In one example, a circuit comprises: a current source having a current output; a switch coupled between the current output and a current terminal, the switch having a switch control input; a pulse signal generator having pulse signal outputs, the pulse signal generator configured to provide pulse signals having different pulse widths at the pulse signal outputs; and a multiplexor circuit having pulse signal inputs, a selection input and a selected pulse signal output, the selected pulse signal output coupled to the switch control input, and the pulse signal inputs coupled to the pulse signal outputs.