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公开(公告)号：US10601408B2
公开(公告)日：2020-03-24
申请号：US15952549
申请日：2018-04-13
Applicant: Texas Instruments Incorporated
Abstract: In described examples, a sawtooth waveform generator generates a sawtooth waveform having a first rise time. A comb waveform circuit has a power terminal coupled to receive the sawtooth waveform from an output of the sawtooth waveform generator. The comb waveform circuit generates a comb waveform in response to the sawtooth waveform. The comb waveform has a second rise time that is faster than the first rise time.
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公开(公告)号：US10547859B2
公开(公告)日：2020-01-28
申请号：US15653561
申请日：2017-07-19
Applicant: Texas Instruments Incorporated
Inventor： Hetul Sanghvi , Mihir Narendra Mody , Niraj Nandan , Mahesh Madhukar Mehendale , Subrangshu Das , Dipan Kumar Mandal , Nainala Vyagrheswarudu , Vijayavardhan Baireddy , Pavan Venkata Shastry
Abstract: A video hardware engine which support dynamic frame padding is disclosed. The video hardware engine includes an external memory. The external memory stores a reference frame. The reference frame includes a plurality of reference pixels. A motion estimation (ME) engine receives a current LCU (largest coding unit), and defines a search area around the current LCU for motion estimation. The ME engine receives a set of reference pixels corresponding to the current LCU. The set of reference pixels of the plurality of reference pixels are received from the external memory. The ME engine pads a set of duplicate pixels along an edge of the reference frame when a part area of the search area is outside the reference frame.
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公开(公告)号：US20150296212A1
公开(公告)日：2015-10-15
申请号：US14684334
申请日：2015-04-11
Applicant: Texas Instruments Incorporated
Inventor： Dipan Kumar Mandal , Mihir Narendra Mody , Mahesh Madhukar Mehendale , Chaitanya Satish Ghone , Piyali Goswami , Naresh Kumar Yadav , Hetul Sanghvi , Niraj Nandan
IPC: H04N19/42 , G06F9/30 , H04N19/463 , G06F9/38
CPC classification number: H04N19/42 , G06F9/30181 , G06F9/3885 , H04N19/43 , H04N19/463
Abstract: A control processor for a video encode-decode engine is provided that includes an instruction pipeline. The instruction pipeline includes an instruction fetch stage coupled to an instruction memory to fetch instructions, an instruction decoding stage coupled to the instruction fetch stage to receive the fetched instructions, and an execution stage coupled to the instruction decoding stage to receive and execute decoded instructions. The instruction decoding stage and the instruction execution stage are configured to decode and execute a set of instructions in an instruction set of the control processor that are designed specifically for accelerating video sequence encoding and encoded video bit stream decoding.
Abstract translation: 提供了一种用于视频编码解码引擎的控制处理器，其包括指令流水线。 指令流水线包括与指令存储器耦合以取指令的指令提取级，耦合到指令提取级以接收所取指令的指令解码级，以及耦合到指令解码级的接收和执行解码指令的执行级。 指令解码级和指令执行级被配置为解码和执行专门用于加速视频序列编码和编码视频位流解码的控制处理器的指令集中的一组指令。
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公开(公告)号：US12094524B2
公开(公告)日：2024-09-17
申请号：US17162694
申请日：2021-01-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Avishek Biswas , Mahesh Madhukar Mehendale , Hetul Sanghvi
IPC: G11C11/4094 , G06G7/16 , G06N3/065 , G11C5/06 , G11C7/10 , G11C11/4074 , G11C11/4097 , G11C11/4099 , G11C11/54
CPC classification number: G11C11/4094 , G06G7/16 , G06N3/065 , G11C5/06 , G11C7/1006 , G11C11/4074 , G11C11/4097 , G11C11/4099 , G11C11/54
Abstract: A device includes a bit cell having first and second terminals, a first bit line coupled to the first terminal, a second bit line coupled to the second terminal, a first capacitor, a second capacitor, and a multiply and average (MAV) circuit coupled to the first capacitor, to the second capacitor, to the first bit line, and to the second bit line. The MAV circuit includes a first transistor coupled to the first capacitor and to a ground terminal and a second transistor coupled to the second capacitor and to the ground terminal. The first transistor has a first transistor control terminal selectively coupled to the first bit line and the second transistor has a second transistor control terminal selectively coupled to the second bit line.
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公开(公告)号：US11445207B2
公开(公告)日：2022-09-13
申请号：US16714837
申请日：2019-12-16
Applicant: Texas Instruments Incorporated
Inventor： Hetul Sanghvi , Mihir Narendra Mody , Niraj Nandan , Mahesh Madhukar Mehendale , Subrangshu Das , Dipan Kumar Mandal , Nainala Vyagrheswarudu , Vijayavardhan Baireddy , Pavan Venkata Shastry
Abstract: A video hardware engine which support dynamic frame padding is disclosed. The video hardware engine includes an external memory. The external memory stores a reference frame. The reference frame includes a plurality of reference pixels. A motion estimation (ME) engine receives a current LCU (largest coding unit), and defines a search area around the current LCU for motion estimation. The ME engine receives a set of reference pixels corresponding to the current LCU. The set of reference pixels of the plurality of reference pixels are received from the external memory. The ME engine pads a set of duplicate pixels along an edge of the reference frame when a part area of the search area is outside the reference frame.
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Patent Agency Ranking
公开(公告)号：US09973754B2
公开(公告)日：2018-05-15
申请号：US14661711
申请日：2015-03-18
Applicant: Texas Instruments Incorporated
Inventor： Hetul Sanghvi , Mihir Narendra Mody , Niraj Nandan , Mahesh Madhukar Mehendale , Subrangshu Das , Dipan Kumar Mandal , Pavan Venkata Shastry
IPC: H04N19/115 , H04N19/423 , G06F13/28
CPC classification number: H04N19/115 , G06F13/28 , H04N19/423
Abstract: A low power video hardware engine is disclosed. The video hardware engine includes a video hardware accelerator unit. A shared memory is coupled to the video hardware accelerator unit, and a scrambler is coupled to the shared memory. A vDMA (video direct memory access) engine is coupled to the scrambler, and an external memory is coupled to the vDMA engine. The scrambler receives an LCU (largest coding unit) from the vDMA engine. The LCU comprises N×N pixels, and the scrambler scrambles N×N pixels in the LCU to generate a plurality of blocks with M×M pixels. N and M are integers and M is less than N.
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公开(公告)号：US11551745B2
公开(公告)日：2023-01-10
申请号：US17162842
申请日：2021-01-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Avishek Biswas , Mahesh Madhukar Mehendale
IPC: G11C5/06 , G11C11/4094 , G11C11/4097 , G11C11/4074 , G11C11/4099 , G06F7/52 , G11C11/54 , G11C7/10 , G06N3/063 , G06N3/04 , G11C7/16 , G11C11/412
Abstract: A device includes a comparator to provide an indication of a difference between Vp on a first terminal coupled to a top plate of each of a first group of differential capacitors, and Vn on a second terminal coupled to a top plate of each of a second group of differential capacitors. The device includes a control circuit coupled to the comparator. The control circuit is to receive a first indication of a difference between Vp and Vn; responsive to the first indication, cause a first driver to provide a reference voltage to bottom plates of one of the first and second groups, and cause a second driver to provide a ground voltage to bottom plates of the other of the first and second groups; receive a second indication of a difference between Vp and Vn; and provide a digital value responsive to the first indication and the second indication.
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公开(公告)号：US20190319614A1
公开(公告)日：2019-10-17
申请号：US15952549
申请日：2018-04-13
Applicant: Texas Instruments Incorporated
Abstract: In described examples, a sawtooth waveform generator generates a sawtooth waveform having a first rise time. A comb waveform circuit has a power terminal coupled to receive the sawtooth waveform from an output of the sawtooth waveform generator. The comb waveform circuit generates a comb waveform in response to the sawtooth waveform. The comb waveform has a second rise time that is faster than the first rise time.
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公开(公告)号：US10447142B1
公开(公告)日：2019-10-15
申请号：US16227314
申请日：2018-12-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Vinod Joseph Menezes , Manikandan RR , Rajat Chauhan , Vipul Kumar Singhal , Mahesh Madhukar Mehendale , Kaichien Tsai
Abstract: A switch-mode power supply includes a DC-DC converter and metering circuitry that is coupled to the DC-DC converter. The metering circuitry includes scaling circuitry, a current source, a capacitor, switching circuitry, and a comparator. The scaling circuitry is configured to generate a reference current scaled to be a predetermined fraction of a peak current flowing in an inductor of the DC-DC converter. The current source is configured to output a first current that is one-half of the reference current. The capacitor is coupled to the current source. The switching circuitry is configured to switchably connect the current source to the capacitor. The comparator is coupled to the capacitor. The comparator is configured to generate a signal indicating that a voltage across the capacitor exceeds a threshold voltage.
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公开(公告)号：US20250029652A1
公开(公告)日：2025-01-23
申请号：US18883541
申请日：2024-09-12
Applicant: Texas Instruments Incorporated
Inventor： Avishek Biswas , Mahesh Madhukar Mehendale , Hetul Sanghvi
IPC: G11C11/4094 , G06G7/16 , G06N3/065 , G11C5/06 , G11C7/10 , G11C11/4074 , G11C11/4097 , G11C11/4099 , G11C11/54
Abstract: A device includes a first bit cell, a second bit cell, and a multiply and average (MAV) circuit. The MAV circuit includes a first selection circuit and a second selection circuit. The first selection circuit has a first selection input and coupled to first and second capacitor terminals, and the first selection circuit is configured to, responsive to a state of the first selection input, set respective states of the first and second capacitor terminals based on a state of the first bit cell. The second selection circuit has a second selection input and is coupled to the first and second capacitor terminals. The second selection circuit is configured to, responsive to a state of the second selection input, set the respective states of the first and second capacitor terminals based on a state of the second bit cell.
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