公开(公告)号：US09899334B1

公开(公告)日：2018-02-20

申请号：US15391742

申请日：2016-12-27

Applicant: Texas Instruments Incorporated

Inventor： Fuchao Wang ,  Prakash Dalpatbhai Dev ,  Dina Rodriguez ,  Dongping Zhang ,  Billy Alan Wofford

IPC: H01L23/544 ,  H01L21/762 ,  H01L21/306 ,  H01L21/311 ,  H01L21/02 ,  H01L21/027

CPC classification number: H01L23/544 ,  H01L21/76202 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: A method includes: growing a oxide layer on a topside of a semiconductor wafer using a local oxidation of silicon (LOCOS) process; forming a photoresist pattern with an alignment opening on the oxide layer; etching the oxide layer to form a trench in the oxide layer; etching an alignment mark trench into the exposed surface of the semiconductor wafer; depositing a dielectric layer that is one of a silicon nitride material or a silicon oxynitride material; performing an anisotropic plasma etch to remove the dielectric layer from horizontal surfaces on the oxide layer and the alignment mark trench and to form sidewalls from the dielectric layer on vertical sidewalls of the alignment mark trench; growing an alignment mark oxide layer on a bottom surface of the alignment trench; and etching and removing the oxide layer and the alignment mark oxide layer.

公开(公告)号：US20240332369A1

公开(公告)日：2024-10-03

申请号：US18193391

申请日：2023-03-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Fuchao Wang ,  Billy Alan Wofford ,  Ebenezer Eshun ,  Jungwoo Joh ,  Dong Seup Lee

IPC: H01L29/20 ,  H01L21/8252 ,  H01L27/088 ,  H01L29/08 ,  H01L29/40

CPC classification number: H01L29/2003 ,  H01L21/8252 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/402

Abstract: In one example, an integrated circuit comprises a transistor and a metal layer. The transistor has an insulator layer over a substrate that includes gallium nitride (GaN). First and second opening in the insulator layer respectively define a drain region and a source region of the transistor. A gate electrode extends into the insulator layer between the source region and the drain region. The metal layer includes a drain via and a source via. The drain via extends through the first opening to the drain region. The source via extends through the second opening to the source region. A source field plate is in the metal layer. The source field plate extends over the gate electrode and provides a contiguous electrically conductive path to the source region.

公开(公告)号：US20180076038A1

公开(公告)日：2018-03-15

申请号：US15260478

申请日：2016-09-09

Applicant: Texas Instruments Incorporated

Inventor： Tony Phan ,  Billy Alan Wofford

IPC: H01L21/225 ,  H01L21/266 ,  H01L29/06 ,  H01L21/265

CPC classification number: H01L29/0684 ,  H01L29/78

Abstract: A method of fabricating an integrated circuit includes forming a patterned dielectric layer, which includes a first pattern of openings, over a substrate and implanting a first n-type dopant into the substrate through the patterned dielectric layer to form a first doped region. The method continues with forming a patterned photoresist layer overlying the patterned dielectric layer, which includes a second pattern of openings and implanting a second n-type dopant into the substrate through the patterned photoresist layer and patterned dielectric layer to form a second doped region. The patterned photoresist layer and patterned dielectric layer are removed. An epitaxial layer is grown on the substrate and the first doped region and second doped region are driven into said epitaxial layer to form respective first and second n-type buried layers, then active devices are formed in the epitaxial layer.