公开(公告)号：US08680618B2

公开(公告)日：2014-03-25

申请号：US13654015

申请日：2012-10-17

Applicant: Texas Instruments Incorporated

Inventor： Ebenezer Eshun

IPC: H01L27/12 ,  H01L49/02 ,  H01L29/8605

CPC classification number: H01L29/8605 ,  H01L27/0629 ,  H01L28/20

Abstract: An integrated circuit having a replacement HiK metal gate transistor and a front end SiCr resistor. The SiCr resistor replaces the conventional polysilicon resistor in front end processing and is integrated into the contact module. The first level of metal interconnect is located above the SiCr resistor. First contacts connect to source/drain regions. Second contacts electrically connect the first level of interconnect to either the SiCr resistor or the metal replacement gate.

Abstract translation: 具有替代的HiK金属栅极晶体管和前端SiCr电阻器的集成电路。 SiCr电阻器替代了前端处理中的常规多晶硅电阻器，并集成到触点模块中。 第一级金属互连位于SiCr电阻上方。 第一个触点连接到源/漏区。 第二触点将第一级互连电连接到SiCr电阻器或金属替代栅极。

公开(公告)号：US20240363691A1

公开(公告)日：2024-10-31

申请号：US18309504

申请日：2023-04-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ebenezer Eshun

IPC: H01L29/10 ,  H01L21/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1095 ,  H01L21/02529 ,  H01L21/0254 ,  H01L21/0262 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/66681 ,  H01L29/7816

Abstract: The present disclosure generally relates to semiconductor devices including a material having a wide bandgap energy, or simply bandgap, located in a drift well of the semiconductor device. In an example, a semiconductor device includes a laterally-diffused metal-oxide-semiconductor (LDMOS) transistor. The LDMOS transistor includes a drain region, a source region, and a drift well. The drain region is disposed in a semiconductor material of a semiconductor substrate. The source region is disposed in the semiconductor material of the semiconductor substrate. The drift well is disposed laterally between the drain region and the source region. The drift well includes a wide bandgap material, and the wide bandgap material has a bandgap energy that is larger than a bandgap energy of the semiconductor material of the semiconductor substrate.

公开(公告)号：US10068802B2

公开(公告)日：2018-09-04

申请号：US13654161

申请日：2012-10-17

Applicant: Texas Instruments Incorporated

Inventor： Ebenezer Eshun ,  Himadri Sekhar Pal ,  Amitabh Jain

IPC: H01L21/8234 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78

Abstract: An integrated circuit containing MOS transistors may be formed using a split carbon co-implantation. The split carbon co-implant includes an angled carbon implant and a zero-degree carbon implant that is substantially perpendicular to a top surface of the integrated circuit. The split carbon co-implant is done at the LDD and halo implant steps.

公开(公告)号：US09431533B2

公开(公告)日：2016-08-30

申请号：US14732769

申请日：2015-06-07

Applicant: Texas Instruments Incorporated

Inventor： Ebenezer Eshun

IPC: H01L21/02 ,  H01L29/78 ,  H01L21/265 ,  H01L21/268 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7836 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/268 ,  H01L29/1083 ,  H01L29/6659

Abstract: An integrated circuit containing an NMOS transistor with a boron-doped halo is formed by co-implanting carbon in at least three angled doses with the boron halo implants. The carbon is co-implanted at tilt angles within 5 degrees of the boron halo implant tilt angle. An implant energy of at least one of the angled carbon co-implant is greater than the implant energy of the boron halo implant. A total carbon dose of the angled carbon co-implants is at least 5 times a total boron dose of the boron halo implants. The NMOS transistor has a carbon concentration in the halo regions which is at least 5 times greater than the boron concentration in the halo regions. The co-implanted carbon extends under the gate of the NMOS transistor.

Abstract translation: 包含硼掺杂卤素的NMOS晶体管的集成电路通过与硼卤素注入物以至少三个成角度的剂量共同植入碳来形成。 碳以与硼卤素注入倾斜角度的5度内的倾斜角度共同植入。 至少一个角度碳共同植入物的植入能量大于硼晕植入物的植入能量。 角度碳共同植入物的总碳剂量是硼卤素植入物的总硼剂量的至少5倍。 NMOS晶体管的卤素区域中的碳浓度比卤素区域中的硼浓度大至少5倍。 共同注入的碳在NMOS晶体管的栅极下方延伸。

公开(公告)号：US20160126108A1

公开(公告)日：2016-05-05

申请号：US14531308

申请日：2014-11-03

Applicant: Texas Instruments Incorporated

Inventor： Ebenezer Eshun

IPC: H01L21/3115 ,  H01L29/51 ,  H01L21/28 ,  H01L21/265

CPC classification number: H01L21/31155 ,  H01L21/02332 ,  H01L21/02351 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28176 ,  H01L29/78

Abstract: In a MOS device, gate leakage is reduced by implanting gate oxide leakage reduction species such as nitrogen into the gate oxide along the edges of the gate to reduce gate leakage and hence reduce data retention fails in SRAM devices and allow low Vdd SRAM operation without increasing gate oxide thickness. By implanting nitrogen along the edges of the gate it simultaneously replaces lost gate oxide nitrogen to further reduce gate leakage.

Abstract translation: 在MOS器件中，通过沿栅极的边缘将栅极氧化物泄漏减少物质（例如氮）注入到栅极氧化物中来减少栅极泄漏，以减少栅极泄漏，从而减少SRAM器件中的数据保留失败，并允许低Vdd SRAM操作而不增加 栅极氧化物厚度。 通过沿着栅极的边缘注入氮气，它同时代替丢失的栅极氧化氮，以进一步减少栅极泄漏。

公开(公告)号：US09202883B2

公开(公告)日：2015-12-01

申请号：US14744384

申请日：2015-06-19

Applicant: Texas Instruments Incorporated

Inventor： Shashank S. Ekbote ,  Kwan-Yong Lim ,  Ebenezer Eshun ,  Youn Sung Choi

IPC: H01L29/08 ,  H01L29/45 ,  H01L29/161 ,  H01L27/088 ,  H01L27/02 ,  H01L21/336

CPC classification number: H01L29/45 ,  H01L21/28123 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823443 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.

Abstract translation: 集成电路包括PMOS栅极结构和相邻场氧化物上的栅极结构。 在场氧化物上的栅极结构上形成外延硬掩模，使得外延硬掩模与PMOS源极/漏极区域中的半导体材料重叠。 SiGe半导体材料在源极/漏极区域中外延形成，使得在场氧化物处的SiGe半导体材料的顶部边缘不超过邻接该场的源极/漏极区域中的SiGe的深度的三分之一以上 氧化物。 场氧化物上的栅极结构的侧表面上的介电隔离物延伸到SiGe上; 至少有三分之一的SiGe被暴露。 金属硅化物覆盖SiGe的顶表面的至少三分之一。 触点具有触点底部的至少一半直接接触SiGe上的金属硅化物。

公开(公告)号：US20240222365A1

公开(公告)日：2024-07-04

申请号：US18148754

申请日：2022-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ebenezer Eshun

IPC: H01L27/06 ,  H01L21/8252

CPC classification number: H01L27/0605 ,  H01L21/8252 ,  H01L28/10

Abstract: An integrated circuit includes a GaN layer located over a semiconductor substrate. The GaN layer includes an active device region of the GaN layer having a first conductivity and a passive device region of the GaN layer having a smaller second conductivity. A transistor may be located over the GaN layer in the active device region, and a passive device may be located over the GaN layer in the passive device region.

公开(公告)号：US20150364600A1

公开(公告)日：2015-12-17

申请号：US14732769

申请日：2015-06-07

Applicant: Texas Instruments Incorporated

Inventor： Ebenezer Eshun

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7836 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/268 ,  H01L29/1083 ,  H01L29/6659

Abstract: An integrated circuit containing an NMOS transistor with a boron-doped halo is formed by co-implanting carbon in at least three angled doses with the boron halo implants. The carbon is co-implanted at tilt angles within 5 degrees of the boron halo implant tilt angle. An implant energy of at least one of the angled carbon co-implant is greater than the implant energy of the boron halo implant. A total carbon dose of the angled carbon co-implants is at least 5 times a total boron dose of the boron halo implants. The NMOS transistor has a carbon concentration in the halo regions which is at least 5 times greater than the boron concentration in the halo regions. The co-implanted carbon extends under the gate of the NMOS transistor.

Abstract translation: 包含硼掺杂卤素的NMOS晶体管的集成电路通过与硼卤素注入物以至少三个成角度的剂量共同植入碳来形成。 碳以与硼卤素注入倾斜角度的5度内的倾斜角度共同植入。 至少一个角度碳共同植入物的植入能量大于硼晕植入物的植入能量。 角度碳共同植入物的总碳剂量是硼卤素植入物的总硼剂量的至少5倍。 NMOS晶体管的卤素区域中的碳浓度比卤素区域中的硼浓度大至少5倍。 共同注入的碳在NMOS晶体管的栅极下方延伸。

公开(公告)号：US20130095630A1

公开(公告)日：2013-04-18

申请号：US13654161

申请日：2012-10-17

Applicant: Texas Instruments Incorporated

Inventor： Ebenezer Eshun ,  Himadri Sekhar Pal ,  Amitabh Jain

IPC: H01L21/266

CPC classification number: H01L21/823412 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823418 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/7833

Abstract: An integrated circuit containing MOS transistors may be formed using a split carbon co-implantation. The split carbon co-implant includes an angled carbon implant and a zero-degree carbon implant that is substantially perpendicular to a top surface of the integrated circuit. The split carbon co-implant is done at the LDD and halo implant steps.

Abstract translation: 可以使用裂缝碳共注入形成包含MOS晶体管的集成电路。 分裂碳共植入物包括角度碳植入物和零度碳植入物，其基本上垂直于集成电路的顶表面。 分裂碳共注入在LDD和晕轮植入步骤完成。

公开(公告)号：US20240332369A1

公开(公告)日：2024-10-03

申请号：US18193391

申请日：2023-03-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Fuchao Wang ,  Billy Alan Wofford ,  Ebenezer Eshun ,  Jungwoo Joh ,  Dong Seup Lee

IPC: H01L29/20 ,  H01L21/8252 ,  H01L27/088 ,  H01L29/08 ,  H01L29/40

CPC classification number: H01L29/2003 ,  H01L21/8252 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/402

Abstract: In one example, an integrated circuit comprises a transistor and a metal layer. The transistor has an insulator layer over a substrate that includes gallium nitride (GaN). First and second opening in the insulator layer respectively define a drain region and a source region of the transistor. A gate electrode extends into the insulator layer between the source region and the drain region. The metal layer includes a drain via and a source via. The drain via extends through the first opening to the drain region. The source via extends through the second opening to the source region. A source field plate is in the metal layer. The source field plate extends over the gate electrode and provides a contiguous electrically conductive path to the source region.