公开(公告)号：US09899334B1

公开(公告)日：2018-02-20

申请号：US15391742

申请日：2016-12-27

Applicant: Texas Instruments Incorporated

Inventor： Fuchao Wang ,  Prakash Dalpatbhai Dev ,  Dina Rodriguez ,  Dongping Zhang ,  Billy Alan Wofford

IPC: H01L23/544 ,  H01L21/762 ,  H01L21/306 ,  H01L21/311 ,  H01L21/02 ,  H01L21/027

CPC classification number: H01L23/544 ,  H01L21/76202 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: A method includes: growing a oxide layer on a topside of a semiconductor wafer using a local oxidation of silicon (LOCOS) process; forming a photoresist pattern with an alignment opening on the oxide layer; etching the oxide layer to form a trench in the oxide layer; etching an alignment mark trench into the exposed surface of the semiconductor wafer; depositing a dielectric layer that is one of a silicon nitride material or a silicon oxynitride material; performing an anisotropic plasma etch to remove the dielectric layer from horizontal surfaces on the oxide layer and the alignment mark trench and to form sidewalls from the dielectric layer on vertical sidewalls of the alignment mark trench; growing an alignment mark oxide layer on a bottom surface of the alignment trench; and etching and removing the oxide layer and the alignment mark oxide layer.

公开(公告)号：US20180166280A1

公开(公告)日：2018-06-14

申请号：US15379251

申请日：2016-12-14

Applicant: Texas Instruments Incorporated

Inventor： Prakash Dalpatbhai Dev ,  Fuchao Wang ,  Nicholas Andrew Kusek

IPC: H01L21/225 ,  H01L21/324 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/2251 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/30655 ,  H01L21/31111 ,  H01L21/324

Abstract: In a described example method, semiconductor wafer with a backside silicon nitride layer is encapsulated with a diffusion barrier layer prior to a high temperature anneal greater than about 1000 degrees Celsius. After the high temperature anneal the diffusion barrier layer and the backside silicon nitride layers are stripped.

公开(公告)号：US10068769B2

公开(公告)日：2018-09-04

申请号：US15379251

申请日：2016-12-14

Applicant: Texas Instruments Incorporated

Inventor： Prakash Dalpatbhai Dev ,  Fuchao Wang ,  Nicholas Andrew Kusek

IPC: H01L21/31 ,  H01L21/225 ,  H01L21/324 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3065

CPC classification number: H01L21/30655 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/26513 ,  H01L21/31111 ,  H01L21/324

Abstract: In a described example method, semiconductor wafer with a backside silicon nitride layer is encapsulated with a diffusion barrier layer prior to a high temperature anneal greater than about 1000 degrees Celsius. After the high temperature anneal the diffusion barrier layer and the backside silicon nitride layers are stripped.