APPARATUS AND MECHANISM TO BYPASS PCIE ADDRESS TRANSLATION BY USING ALTERNATIVE ROUTING

    公开(公告)号:US20230018225A1

    公开(公告)日:2023-01-19

    申请号:US17946270

    申请日:2022-09-16

    Abstract: An address space field is used in conjunction with a normal address field to allow indication of an address space for the particular address value. In one instance, one address space value is used to indicate the bypassing of the address translation used between address spaces. A different address space value is designated for conventional operation, where address translations are performed. Other address space values are used to designate different transformations of the address values or the data. This technique provides a simplified format for handling address values and the like between different devices having different address spaces, simplifying overall computer system design and operation.

    TESTING OF FAULT DETECTION CIRCUIT

    公开(公告)号:US20210375383A1

    公开(公告)日:2021-12-02

    申请号:US17402706

    申请日:2021-08-16

    Abstract: A system-on-chip includes first and second devices. An interconnect segment couples between the first and second devices. A bridge is coupled between the first and second devices and coupled to the interconnect segment. At least one of the bridge or interconnect segment include first and second multiplexers, a monitor circuit, and exclusive-OR logic. The first multiplexer has first and second multiplexer inputs and a first multiplexer output. The second multiplexer has third and fourth multiplexer inputs and a second multiplexer output. The monitor circuit has a first and second monitor circuit outputs. The first monitor circuit output is coupled to the second multiplexer input and the second monitor circuit output is coupled to the fourth multiplexer input. The exclusive-OR logic has first and second exclusive-OR logic inputs. The first exclusive-OR logic input couples to the first multiplexer output and the second exclusive-OR logic input couples to the second multiplexer output.

    APPARATUS AND MECHANISM TO BYPASS PCIE ADDRESS TRANSLATION BY USING ALTERNATIVE ROUTING

    公开(公告)号:US20240394206A1

    公开(公告)日:2024-11-28

    申请号:US18794472

    申请日:2024-08-05

    Abstract: An address space field is used in conjunction with a normal address field to allow indication of an address space for the particular address value. In one instance, one address space value is used to indicate the bypassing of the address translation used between address spaces. A different address space value is designated for conventional operation, where address translations are performed. Other address space values are used to designate different transformations of the address values or the data. This technique provides a simplified format for handling address values and the like between different devices having different address spaces, simplifying overall computer system design and operation.

    Apparatus and Mechanism to Bypass PCIe Address Translation By Using Alternative Routing

    公开(公告)号:US20190391941A1

    公开(公告)日:2019-12-26

    申请号:US16559154

    申请日:2019-09-03

    Abstract: An address space field is used in conjunction with a normal address field to allow indication of an address space for the particular address value. In one instance, one address space value is used to indicate the bypassing of the address translation used between address spaces. A different address space value is designated for conventional operation, where address translations are performed. Other address space values are used to designate different transformations of the address values or the data. This technique provides a simplified format for handling address values and the like between different devices having different address spaces, simplifying overall computer system design and operation.

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