公开(公告)号：US20230350811A1

公开(公告)日：2023-11-02

申请号：US18346309

申请日：2023-07-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan GOVINDARAJAN ,  Gregory Raymond SHURTZ ,  Mihir Narendra MODY ,  Charles Lance FUOCO ,  Donald E. STEISS ,  Jonathan Elliot BERGSAGEL ,  Jason A.T. JONES

IPC: G06F12/1027 ,  G06F9/455

CPC classification number: G06F12/1027 ,  G06F9/45558 ,  G06F2009/45583 ,  G06F2212/657

Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.

公开(公告)号：US20240193112A1

公开(公告)日：2024-06-13

申请号：US18581522

申请日：2024-02-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Brian Jason KARGUTH ,  Charles Lance FUOCO ,  Samuel Paul VISALLI ,  Michael Anthony DENIO

IPC: G06F13/28 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F13/4027

Abstract: An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits.

公开(公告)号：US20200242048A1

公开(公告)日：2020-07-30

申请号：US16256821

申请日：2019-01-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan GOVINDARAJAN ,  Gregory Raymond SHURTZ ,  Mihir Narendra MODY ,  Charles Lance FUOCO ,  Donald E. STEISS ,  Jonathan Elliot BERGSAGEL ,  Jason A.T. JONES

IPC: G06F12/1027 ,  G06F9/455

Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.

公开(公告)号：US20210165744A1

公开(公告)日：2021-06-03

申请号：US17171185

申请日：2021-02-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan GOVINDARAJAN ,  Gregory Raymond SHURTZ ,  Mihir Narendra MODY ,  Charles Lance FUOCO ,  Donald E. STEISS ,  Jonathan Elliot BERGSAGEL ,  Jason A.T. JONES

IPC: G06F12/1027 ,  G06F9/455

Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.

公开(公告)号：US20210073150A1

公开(公告)日：2021-03-11

申请号：US17099896

申请日：2020-11-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Brian Jason KARGUTH ,  Charles Lance FUOCO ,  Samuel Paul VISALLI ,  Michael Anthony DENIO

IPC: G06F13/28 ,  G06F13/40

Abstract: An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits.

公开(公告)号：US20230042413A1

公开(公告)日：2023-02-09

申请号：US17971707

申请日：2022-10-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Brian Jason KARGUTH ,  Charles Lance FUOCO ,  Samuel Paul VISALLI ,  Michael Anthony DENIO

IPC: G06F13/28 ,  G06F13/40

Abstract: An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits.

公开(公告)号：US20210375383A1

公开(公告)日：2021-12-02

申请号：US17402706

申请日：2021-08-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Charles Lance FUOCO ,  Brian KARGUTH ,  Jay Bryan REIMER ,  Samuel Paul VISALLI

IPC: G11C29/42 ,  G06F9/30 ,  G06F11/10

Abstract: A system-on-chip includes first and second devices. An interconnect segment couples between the first and second devices. A bridge is coupled between the first and second devices and coupled to the interconnect segment. At least one of the bridge or interconnect segment include first and second multiplexers, a monitor circuit, and exclusive-OR logic. The first multiplexer has first and second multiplexer inputs and a first multiplexer output. The second multiplexer has third and fourth multiplexer inputs and a second multiplexer output. The monitor circuit has a first and second monitor circuit outputs. The first monitor circuit output is coupled to the second multiplexer input and the second monitor circuit output is coupled to the fourth multiplexer input. The exclusive-OR logic has first and second exclusive-OR logic inputs. The first exclusive-OR logic input couples to the first multiplexer output and the second exclusive-OR logic input couples to the second multiplexer output.

公开(公告)号：US20200210256A1

公开(公告)日：2020-07-02

申请号：US16377404

申请日：2019-04-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kedar Satish CHITNIS ,  Charles Lance FUOCO ,  Sriramakrishnan GOVINDARAJAN ,  Mihir Narendra MODY ,  William A. MILLS ,  Gregory Raymond SHURTZ ,  Amritpal Singh MUNDRA

IPC: G06F9/54 ,  G06F9/50 ,  G06F9/38 ,  G06F9/48 ,  G06F9/455

Abstract: This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.