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    APPARATUS AND MECHANISM TO SUPPORT MULTIPLE TIME DOMAINS IN A SINGLE SOC FOR TIME SENSITIVE NETWORK
    1.
    发明申请
    APPARATUS AND MECHANISM TO SUPPORT MULTIPLE TIME DOMAINS IN A SINGLE SOC FOR TIME SENSITIVE NETWORK 审中-公开

    公开(公告)号：US20200059311A1

    公开(公告)日：2020-02-20

    申请号：US16552353

    申请日：2019-08-27

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Chunhua HU ,  Venkateswar Reddy KOWKUTLA ,  Eric HANSEN ,  Denis BEAUDOIN ,  Thomas Anton LEYRER

    IPC: H04J3/06

    Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

    APPARATUS AND MECHANISM TO BYPASS PCIE ADDRESS TRANSLATION BY USING ALTERNATIVE ROUTING
    2.
    发明申请
    APPARATUS AND MECHANISM TO BYPASS PCIE ADDRESS TRANSLATION BY USING ALTERNATIVE ROUTING 有权

    公开(公告)号：US20230018225A1

    公开(公告)日：2023-01-19

    申请号：US17946270

    申请日：2022-09-16

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Brian KARGUTH ,  Chuck FUOCO ,  Chunhua HU ,  Todd Christopher HIERS

    IPC: G06F13/28 ,  G06F12/1081 ,  G06F13/42

    Abstract: An address space field is used in conjunction with a normal address field to allow indication of an address space for the particular address value. In one instance, one address space value is used to indicate the bypassing of the address translation used between address spaces. A different address space value is designated for conventional operation, where address translations are performed. Other address space values are used to designate different transformations of the address values or the data. This technique provides a simplified format for handling address values and the like between different devices having different address spaces, simplifying overall computer system design and operation.

    LATENCY AND JITTER FOR TRAFFIC OVER PCIE
    3.
    发明申请
    LATENCY AND JITTER FOR TRAFFIC OVER PCIE 有权

    公开(公告)号：US20220206977A1

    公开(公告)日：2022-06-30

    申请号：US17139441

    申请日：2020-12-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Chunhua HU ,  Sanand PRASAD

    IPC: G06F13/28 ,  G06F13/42

    Abstract: A method includes transmitting first data with a first priority through a first dedicated interface on a transmit side of a PCIe system. The method also includes transmitting second data with a second priority through a second dedicated interface on the transmit side of the PCIe system. The method includes transmitting the first data and the second data to a receive side of the PCIe system using two or more virtual channels over a PCIe link, where the first data uses a first virtual channel and the second data uses a second virtual channel.

    TRANSMIT AND RECEIVE CIRCUITS WITH MULTIPLE INTERFACES
    4.
    发明公开
    TRANSMIT AND RECEIVE CIRCUITS WITH MULTIPLE INTERFACES 审中-公开

    公开(公告)号：US20240012774A1

    公开(公告)日：2024-01-11

    申请号：US18473391

    申请日：2023-09-25

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Chunhua HU ,  Sanand PRASAD

    IPC: G06F13/16 ,  G06F13/40

    CPC classification number: G06F13/1668 ,  G06F13/4022

    Abstract: A method includes transmitting first data with a first priority through a first dedicated interface on a transmit side of a PCIe system. The method also includes transmitting second data with a second priority through a second dedicated interface on the transmit side of the PCIe system. The method includes transmitting the first data and the second data to a receive side of the PCIe system using two or more virtual channels over a PCIe link, where the first data uses a first virtual channel and the second data uses a second virtual channel.

    APPARATUS AND MECHANISM TO SUPPORT MULTIPLE TIME DOMAINS IN A SINGLE SOC FOR TIME SENSITIVE NETWORK
    5.
    发明申请
    APPARATUS AND MECHANISM TO SUPPORT MULTIPLE TIME DOMAINS IN A SINGLE SOC FOR TIME SENSITIVE NETWORK 有权

    公开(公告)号：US20220368444A1

    公开(公告)日：2022-11-17

    申请号：US17876662

    申请日：2022-07-29

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Chunhua HU ,  Venkateswar Reddy KOWKUTLA ,  Eric HANSEN ,  Denis BEAUDOIN ,  Thomas Anton LEYRER

    IPC: H04J3/06

    Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

    APPARATUS AND MECHANISM TO BYPASS PCIE ADDRESS TRANSLATION BY USING ALTERNATIVE ROUTING
    8.
    发明申请
    APPARATUS AND MECHANISM TO BYPASS PCIE ADDRESS TRANSLATION BY USING ALTERNATIVE ROUTING 有权

    公开(公告)号：US20240394206A1

    公开(公告)日：2024-11-28

    申请号：US18794472

    申请日：2024-08-05

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Brian KARGUTH ,  Chuck FUOCO ,  Chunhua HU ,  Todd Christopher HIERS

    IPC: G06F13/28 ,  G06F12/1081 ,  G06F13/42

    Abstract: An address space field is used in conjunction with a normal address field to allow indication of an address space for the particular address value. In one instance, one address space value is used to indicate the bypassing of the address translation used between address spaces. A different address space value is designated for conventional operation, where address translations are performed. Other address space values are used to designate different transformations of the address values or the data. This technique provides a simplified format for handling address values and the like between different devices having different address spaces, simplifying overall computer system design and operation.

    Apparatus and Mechanism to Bypass PCIe Address Translation By Using Alternative Routing
    9.
    发明申请
    Apparatus and Mechanism to Bypass PCIe Address Translation By Using Alternative Routing 审中-公开

    公开(公告)号：US20190391941A1

    公开(公告)日：2019-12-26

    申请号：US16559154

    申请日：2019-09-03

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Brian KARGUTH ,  Chuck FUOCO ,  Chunhua HU ,  Todd Christopher HIERS

    IPC: G06F13/28 ,  G06F12/1081 ,  G06F13/42

    Abstract: An address space field is used in conjunction with a normal address field to allow indication of an address space for the particular address value. In one instance, one address space value is used to indicate the bypassing of the address translation used between address spaces. A different address space value is designated for conventional operation, where address translations are performed. Other address space values are used to designate different transformations of the address values or the data. This technique provides a simplified format for handling address values and the like between different devices having different address spaces, simplifying overall computer system design and operation.

    SYSTEM-ON-CHIP (SoC) ASSEMBLY, CONFIGURABLE IP GENERATION AND IP INTEGRATION UTILIZING DISTRIBUTED COMPUTER SYSTEMS
    10.
    发明申请
    SYSTEM-ON-CHIP (SoC) ASSEMBLY, CONFIGURABLE IP GENERATION AND IP INTEGRATION UTILIZING DISTRIBUTED COMPUTER SYSTEMS 审中-公开

    公开(公告)号：US20180212839A1

    公开(公告)日：2018-07-26

    申请号：US15878978

    申请日：2018-01-24

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Todd Christopher HIERS ,  Chunhua HU

    IPC: H04L12/24 ,  G06F3/0486 ,  G06F3/0483

    CPC classification number: H04L41/22 ,  G06F3/0483 ,  G06F3/0486 ,  G06F17/5045 ,  H04L41/12

    Abstract: An architecture-specific web-based executable specification tool maintains specification information and metadata for chip and system on a chip (SoC) design. Metadata available in the development ecosystem may be leveraged to improve the specification-to-design process. A unified, integrated environment for subsystem creation, SoC integration, and SoC specification teams is presented using a tool that comprehends SoC constructs. A modern web-based framework (not stand-alone tool) provides collaboration capabilities and allows visual representation and manipulation of data. Connection fabrics (e.g., network on a chip (NoC)) and other project-specific infrastructure can be configured and synthesized on demand and brought in to the design using the common environment. Netlists and other connectivity data can be fed into automated RTL generation processes directly, or used as a reference for implementation design teams. Reports and automated software generation satisfy the needs of the design verification and software teams. Functional and performance testing feedback loops are also provided.

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