公开(公告)号：US20240363748A1

公开(公告)日：2024-10-31

申请号：US18309792

申请日：2023-04-29

Applicant: Texas Instruments Incorporated

Inventor： Dhanoop Varghese ,  Henry Litzmann Edwards ,  Pinghai Hao

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/4238 ,  H01L29/66681

Abstract: Semiconductor devices including selectively doped gate electrodes are described. The semiconductor device comprises a substrate including a body region and a drift region, a gate dielectric layer on the substrate, the gate dielectric layer extending over the body region and the drift region, and a gate dielectric layer on the drift region, the field relief dielectric layer laterally abutting the gate dielectric layer at a location in the drift region. The semiconductor device also includes a gate electrode having an n-doped first portion, a p-doped second portion, and an n-doped third portion. The selectively doped second portion of the gate electrode is located over an intersection between the gate dielectric layer and the field relief dielectric layer.

公开(公告)号：US20200058485A1

公开(公告)日：2020-02-20

申请号：US16542628

申请日：2019-08-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Alan West ,  Adrian Salinas ,  Elizabeth C. Stewart ,  Dhanoop Varghese ,  Thomas D. Bonifield

IPC: H01L21/02 ,  H01L49/02

Abstract: An integrated circuit a semiconductor substrate includes a device die with includes transistors configured to execute an electrical function. A first interconnect layer of the device die is configured to route electrical signals or power to terminals of the transistors. An interlevel dielectric (ILD) layer is located over the interconnect layer. A metal electrode located over the ILD layer. A dielectric barrier layer is located between the ILD layer and the metal electrode. A scribe seal surrounds the device die. A first opening within the dielectric barrier layer surrounds the metal electrode. Second and third openings within the dielectric barrier layer are located between the first opening and the scribe seal.

公开(公告)号：US10886120B2

公开(公告)日：2021-01-05

申请号：US16542628

申请日：2019-08-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Alan West ,  Adrian Salinas ,  Elizabeth C. Stewart ,  Dhanoop Varghese ,  Thomas D. Bonifield

IPC: H01L21/02 ,  H01L49/02

Abstract: An integrated circuit a semiconductor substrate includes a device die with includes transistors configured to execute an electrical function. A first interconnect layer of the device die is configured to route electrical signals or power to terminals of the transistors. An interlevel dielectric (ILD) layer is located over the interconnect layer. A metal electrode located over the ILD layer. A dielectric barrier layer is located between the ILD layer and the metal electrode. A scribe seal surrounds the device die. A first opening within the dielectric barrier layer surrounds the metal electrode. Second and third openings within the dielectric barrier layer are located between the first opening and the scribe seal.

公开(公告)号：US20200006549A1

公开(公告)日：2020-01-02

申请号：US16021601

申请日：2018-06-28

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Andrew Derek Strachan ,  Henry Litzmann Edwards ,  Dhanoop Varghese ,  Xiaoju Wu ,  Binghua Hu ,  James Robert Todd

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L21/266 ,  H01L21/265

Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods in which an oxide structure is formed over a drift region of a semiconductor substrate, and a shallow implantation process is performed using a first mask that exposes the oxide structure and a first portion of the semiconductor substrate to form a first drift region portion for connection to a body implant region. A second drift region portion is implanted in the semiconductor substrate under the oxide structure by a second implantation process using the first mask at a higher implant energy.

公开(公告)号：US20230361222A1

公开(公告)日：2023-11-09

申请号：US17737515

申请日：2022-05-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sagnik Dey ,  Dhanoop Varghese ,  Dong Seup Lee

IPC: H01L29/8605 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

CPC classification number: H01L29/8605 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66196 ,  H01L29/66166

Abstract: The present disclosure generally relates to a resistor structure having a charge control layer. In an example, an integrated circuit includes a semiconductor substrate, a dielectric layer, a first contact, a second contact, and a charge control layer. The semiconductor substrate includes a semiconductor hetero-structure. The dielectric layer is disposed over the semiconductor substrate. The first contact is disposed through the dielectric layer and contacting the semiconductor hetero-structure. The second contact is disposed through the dielectric layer and contacting the semiconductor hetero-structure. The second contact is disposed laterally separated from the first contact. The charge control layer is disposed over the semiconductor hetero-structure and laterally between the first contact and the second contact. At least a portion of the dielectric layer is disposed between the charge control layer and the semiconductor hetero-structure.

公开(公告)号：US11152505B2

公开(公告)日：2021-10-19

申请号：US16021601

申请日：2018-06-28

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Andrew Derek Strachan ,  Henry Litzmann Edwards ,  Dhanoop Varghese ,  Xiaoju Wu ,  Binghua Hu ,  James Robert Todd

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/265 ,  H01L29/08 ,  H01L21/266

Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods in which an oxide structure is formed over a drift region of a semiconductor substrate, and a shallow implantation process is performed using a first mask that exposes the oxide structure and a first portion of the semiconductor substrate to form a first drift region portion for connection to a body implant region. A second drift region portion is implanted in the semiconductor substrate under the oxide structure by a second implantation process using the first mask at a higher implant energy.