公开(公告)号：US10886120B2

公开(公告)日：2021-01-05

申请号：US16542628

申请日：2019-08-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Alan West ,  Adrian Salinas ,  Elizabeth C. Stewart ,  Dhanoop Varghese ,  Thomas D. Bonifield

IPC: H01L21/02 ,  H01L49/02

Abstract: An integrated circuit a semiconductor substrate includes a device die with includes transistors configured to execute an electrical function. A first interconnect layer of the device die is configured to route electrical signals or power to terminals of the transistors. An interlevel dielectric (ILD) layer is located over the interconnect layer. A metal electrode located over the ILD layer. A dielectric barrier layer is located between the ILD layer and the metal electrode. A scribe seal surrounds the device die. A first opening within the dielectric barrier layer surrounds the metal electrode. Second and third openings within the dielectric barrier layer are located between the first opening and the scribe seal.

公开(公告)号：US11094644B2

公开(公告)日：2021-08-17

申请号：US16679997

申请日：2019-11-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Adrian Salinas ,  William Keith McDonald ,  Scott Alexander Johannesmeyer ,  Robert Paul Luckin ,  Stephen Arlon Meisner

IPC: G03F7/20 ,  H01L21/027 ,  H01L23/544

Abstract: In examples, a method of manufacturing an integrated circuit comprises locating a photomask between a light source and a semiconductor wafer having a photoresist layer in a wafer scribe lane of the wafer, wherein the photomask comprises: a first mask scribe lane pattern; a second mask scribe lane pattern matching the first mask scribe lane pattern; and at least one circuit pattern of the integrated circuit located between the first and second mask scribe lane patterns. The method further includes illuminating the photomask to produce in the photoresist layer of the wafer scribe lane a first exposed portion corresponding to the second mask scribe lane pattern; locating the first mask scribe lane pattern between the light source and the first exposed portion; and illuminating the photomask, wherein the first mask scribe lane pattern substantially shields non-exposed portions of the photoresist layer of the wafer scribe lane from light exposure.

公开(公告)号：US20200058485A1

公开(公告)日：2020-02-20

申请号：US16542628

申请日：2019-08-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Alan West ,  Adrian Salinas ,  Elizabeth C. Stewart ,  Dhanoop Varghese ,  Thomas D. Bonifield

IPC: H01L21/02 ,  H01L49/02

Abstract: An integrated circuit a semiconductor substrate includes a device die with includes transistors configured to execute an electrical function. A first interconnect layer of the device die is configured to route electrical signals or power to terminals of the transistors. An interlevel dielectric (ILD) layer is located over the interconnect layer. A metal electrode located over the ILD layer. A dielectric barrier layer is located between the ILD layer and the metal electrode. A scribe seal surrounds the device die. A first opening within the dielectric barrier layer surrounds the metal electrode. Second and third openings within the dielectric barrier layer are located between the first opening and the scribe seal.