公开(公告)号：US10886120B2

公开(公告)日：2021-01-05

申请号：US16542628

申请日：2019-08-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Alan West ,  Adrian Salinas ,  Elizabeth C. Stewart ,  Dhanoop Varghese ,  Thomas D. Bonifield

IPC: H01L21/02 ,  H01L49/02

Abstract: An integrated circuit a semiconductor substrate includes a device die with includes transistors configured to execute an electrical function. A first interconnect layer of the device die is configured to route electrical signals or power to terminals of the transistors. An interlevel dielectric (ILD) layer is located over the interconnect layer. A metal electrode located over the ILD layer. A dielectric barrier layer is located between the ILD layer and the metal electrode. A scribe seal surrounds the device die. A first opening within the dielectric barrier layer surrounds the metal electrode. Second and third openings within the dielectric barrier layer are located between the first opening and the scribe seal.

公开(公告)号：US20200058485A1

公开(公告)日：2020-02-20

申请号：US16542628

申请日：2019-08-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Alan West ,  Adrian Salinas ,  Elizabeth C. Stewart ,  Dhanoop Varghese ,  Thomas D. Bonifield

IPC: H01L21/02 ,  H01L49/02

Abstract: An integrated circuit a semiconductor substrate includes a device die with includes transistors configured to execute an electrical function. A first interconnect layer of the device die is configured to route electrical signals or power to terminals of the transistors. An interlevel dielectric (ILD) layer is located over the interconnect layer. A metal electrode located over the ILD layer. A dielectric barrier layer is located between the ILD layer and the metal electrode. A scribe seal surrounds the device die. A first opening within the dielectric barrier layer surrounds the metal electrode. Second and third openings within the dielectric barrier layer are located between the first opening and the scribe seal.

公开(公告)号：US11087451B2

公开(公告)日：2021-08-10

申请号：US15847600

申请日：2017-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Elizabeth C. Stewart ,  Young Sawk Oh ,  Zhiyi Yu ,  Jeffrey A. West ,  Thomas D. Bonifield

IPC: G06K9/00 ,  G06T7/00

Abstract: A method comprises obtaining a wafer comprising a plurality of components, wherein each of the plurality of components exposes a first surface of the component present in a first focal plane and a second surface of the component present in a second focal plane. The method comprises generating, by an optical tool, a first image of the first surface and a second image of the second surface of one of the plurality of components. The method comprises comparing, by a processor, the first image with a first reference image to produce a first value and the second image with a second reference image to produce a second value. The method comprises generating, by the processor, a wafer map indicating a quality state of the one of the plurality of components based on the first and second values.

公开(公告)号：US11205695B2

公开(公告)日：2021-12-21

申请号：US15850999

申请日：2017-12-21

Applicant: Texas Instruments Incorporated

Inventor： Elizabeth C. Stewart ,  Jeffrey Alan West ,  Thomas D. Bonifield ,  Jay Sung Chun ,  Byron Lovell Williams

IPC: H01L21/02 ,  H01L23/522 ,  H01L49/02 ,  H01L21/027 ,  H01L21/311

Abstract: Methods of fabricating a thick oxide feature on a semiconductor wafer include forming a oxide layer having a thickness of at least six micrometers and depositing a photoresist layer on the oxide layer. The oxide layer has a first etch rate of X with a given etchant, the photoresist layer has a second etch rate of Y with the given etchant and the ratio of X:Y is less than 4:1. Prior to etching the photoresist layer and the oxide layer, the photoresist layer is patterned with a grayscale mask that creates a photoresist layer having a sidewall that forms an angle with the horizontal that is less than or equal to 10 degrees.

公开(公告)号：US20190198604A1

公开(公告)日：2019-06-27

申请号：US15850999

申请日：2017-12-21

Applicant: Texas Instruments Incorporated

Inventor： Elizabeth C. Stewart ,  Jeffrey Alan West ,  Thomas D. Bonifield ,  Jay Sung Chun ,  Byron Lovell Williams

IPC: H01L49/02 ,  H01L21/027 ,  H01L21/311 ,  H01L21/02 ,  H01L23/522

CPC classification number: H01L28/40 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L23/5223

Abstract: Methods of fabricating a thick oxide feature on a semiconductor wafer include forming a oxide layer having a thickness of at least six micrometers and depositing a photoresist layer on the oxide layer. The oxide layer has a first etch rate of X with a given etchant, the photoresist layer has a second etch rate of Y with the given etchant and the ratio of X:Y is less than 4:1. Prior to etching the photoresist layer and the oxide layer, the photoresist layer is patterned with a grayscale mask that creates a photoresist layer having a sidewall that forms an angle with the horizontal that is less than or equal to 10 degrees.