公开(公告)号：US20200371790A1

公开(公告)日：2020-11-26

申请号：US16786457

申请日：2020-02-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Duc Quang BUI ,  Alan L. DAVIS ,  Dheera Balasubramanian SAMUDRALA ,  Timothy David ANDERSON

IPC: G06F9/30 ,  G06F9/38

Abstract: A method of storing register data elements to interleave with data elements of a different register, a processor thereof, and a system thereof, wherein each non-consecutive data elements of a register is retrieved to be stored to interleave with each non-consecutive data elements of a different register upon an executive of an interleaving store instruction, wherein a mask instruction directing a lane of a storage space in which the non-consecutive data elements are stored is executed in conjunction with the interleaving store instruction, and wherein a processor of a second type is configured to emulate a processor of a first type to store the non-consecutive data elements the same as non-consecutive data elements stored in the first type processor.

公开(公告)号：US20200379757A1

公开(公告)日：2020-12-03

申请号：US16570931

申请日：2019-09-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Duc BUI ,  Rama VENKATASUBRAMANIAN ,  Dheera Balasubramanian SAMUDRALA ,  Alan DAVIS

IPC: G06F9/30 ,  G06F9/38

Abstract: A digital data processor includes an instruction memory storing instructions each specifying a data processing operation and at least one data operand field, an instruction decoder coupled to the instruction memory for sequentially recalling instructions from the instruction memory and determining the data processing operation and the at least one data operand, and at least one operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon at least one operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to increment histogram values in response to a histogram instruction by incrementing a bin entry at a specified location in a specified number of at least one histogram.

公开(公告)号：US20200371795A1

公开(公告)日：2020-11-26

申请号：US16422719

申请日：2019-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph ZBICIAK ,  Dheera Balasubramanian SAMUDRALA ,  Duc BUI

IPC: G06F9/30 ,  G06F7/78

Abstract: A method to transpose source data in a processor in response to a vector bit transpose instruction includes specifying, in respective fields of the vector bit transpose instruction, a source register containing the source data and a destination register to store transposed data. The method also includes executing the vector bit transpose instruction by interpreting N×N bits of the source data as a two-dimensional array having N rows and N columns, creating transposed source data by transposing the bits by reversing a row index and a column index for each bit, and storing the transposed source data in the destination register.

公开(公告)号：US20220188113A1

公开(公告)日：2022-06-16

申请号：US17686584

申请日：2022-03-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Duc BUI ,  Dheera Balasubramanian SAMUDRALA

IPC: G06F9/30 ,  G11C11/409 ,  G06F12/02 ,  G06F16/31 ,  G06F16/901 ,  G06F16/41 ,  G06F9/445 ,  G06F9/38

Abstract: A digital data processor includes an instruction memory storing instructions each specifying a data processing operation and at least one data operand field, an instruction decoder coupled to the instruction memory for sequentially recalling instructions from the instruction memory and determining the data processing operation and the at least one data operand, and at least one operational unit coupled to a data register file and to the instruction decoder to perform a data processing operation upon at least one operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The at least one operational unit is configured to perform a table write in response to a look up table write instruction by writing at least one data element from a source data register to a specified location in a specified number of at least one table.

公开(公告)号：US20200380035A1

公开(公告)日：2020-12-03

申请号：US16570874

申请日：2019-09-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Duc BUI ,  Dheera Balasubramanian SAMUDRALA ,  Rama VENKATASUBRAMANIAN

IPC: G06F16/901 ,  G06F9/445 ,  G06F16/41 ,  G06F16/31

Abstract: A digital data processor includes a multi-stage butterfly network, which is configured to, in response to a look up table read instruction, receive look up table data from an intermediate register, reorder the look up table data based on control signals comprising look up table configuration register data, and write the reordered look up table data to a destination register specified by the look up table read instruction.

公开(公告)号：US20200379763A1

公开(公告)日：2020-12-03

申请号：US16570778

申请日：2019-09-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Dheera Balasubramanian SAMUDRALA ,  Duc BUI ,  Rama VENKATASUBRAMANIAN

IPC: G06F9/30 ,  G06F12/02 ,  G11C11/409

Abstract: A digital data processor includes an instruction memory storing instructions specifying a data processing operation and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to perform a table write in response to a look up table initialization instruction by duplicating at least one data element from a source data register to create duplicated data elements, and writing the duplicated data elements to a specified location in a specified number of at least one table and a corresponding location in at least one other table.

公开(公告)号：US20240020125A1

公开(公告)日：2024-01-18

申请号：US18477657

申请日：2023-09-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Duc BUI ,  Dheera Balasubramanian SAMUDRALA ,  Rama VENKATASUBRAMANIAN

IPC: G06F9/30 ,  G11C11/409 ,  G06F12/02 ,  G06F9/38 ,  G06F16/31 ,  G06F16/901 ,  G06F16/41 ,  G06F9/445

CPC classification number: G06F9/30145 ,  G06F9/30105 ,  G11C11/409 ,  G06F12/0246 ,  G06F12/0292 ,  G06F9/30007 ,  G06F9/3001 ,  G06F9/30101 ,  G06F9/3818 ,  G06F9/30043 ,  G06F9/30032 ,  G06F16/322 ,  G06F16/9017 ,  G06F16/41 ,  G06F9/44505 ,  G06F3/0647

Abstract: A digital data processor includes a multi-stage butterfly network, which is configured to, in response to a look up table read instruction, receive look up table data from an intermediate register, reorder the look up table data based on control signals comprising look up table configuration register data, and write the reordered look up table data to a destination register specified by the look up table read instruction.

公开(公告)号：US20230043776A1

公开(公告)日：2023-02-09

申请号：US17952517

申请日：2022-09-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Dheera Balasubramanian SAMUDRALA ,  Duc BUI ,  Alan DAVIS

IPC: G06F9/30 ,  G11C11/409 ,  G06F12/02 ,  G06F16/31 ,  G06F16/901 ,  G06F16/41 ,  G06F9/445 ,  G06F9/38

Abstract: A digital data processor includes an instruction memory storing instructions specifying data processing operations and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and an instruction decoder to perform an operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the operation. The operational unit is configured to perform a table recall in response to a look up table read instruction by recalling data elements from a specified location and adjacent location to the specified location, in a specified number of at least one table and storing the recalled data elements in successive slots in a destination register. Recalled data elements include at least one interpolated data element in the adjacent location.

公开(公告)号：US20200379762A1

公开(公告)日：2020-12-03

申请号：US16570640

申请日：2019-09-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Dheera Balasubramanian SAMUDRALA ,  Duc BUI ,  Alan DAVIS

IPC: G06F9/30 ,  G06F12/02 ,  G11C11/409

Abstract: A digital data processor includes an instruction memory storing instructions specifying data processing operations and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and an instruction decoder to perform an operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the operation. The operational unit is configured to perform a table recall in response to a look up table read instruction by recalling data elements from a specified location and adjacent location to the specified location, in a specified number of at least one table and storing the recalled data elements in successive slots in a destination register. Recalled data elements include at least one interpolated data element in the adjacent location.

公开(公告)号：US20200379761A1

公开(公告)日：2020-12-03

申请号：US16570519

申请日：2019-09-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Duc BUI ,  Dheera Balasubramanian SAMUDRALA

IPC: G06F9/30 ,  G06F12/02 ,  G11C11/409

Abstract: A digital data processor includes an instruction memory storing instructions each specifying a data processing operation and at least one data operand field, an instruction decoder coupled to the instruction memory for sequentially recalling instructions from the instruction memory and determining the data processing operation and the at least one data operand, and at least one operational unit coupled to a data register file and to the instruction decoder to perform a data processing operation upon at least one operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The at least one operational unit is configured to perform a table write in response to a look up table write instruction by writing at least one data element from a source data register to a specified location in a specified number of at least one table.