公开(公告)号：US20200379757A1

公开(公告)日：2020-12-03

申请号：US16570931

申请日：2019-09-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Duc BUI ,  Rama VENKATASUBRAMANIAN ,  Dheera Balasubramanian SAMUDRALA ,  Alan DAVIS

IPC: G06F9/30 ,  G06F9/38

Abstract: A digital data processor includes an instruction memory storing instructions each specifying a data processing operation and at least one data operand field, an instruction decoder coupled to the instruction memory for sequentially recalling instructions from the instruction memory and determining the data processing operation and the at least one data operand, and at least one operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon at least one operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to increment histogram values in response to a histogram instruction by incrementing a bin entry at a specified location in a specified number of at least one histogram.

公开(公告)号：US20200371795A1

公开(公告)日：2020-11-26

申请号：US16422719

申请日：2019-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph ZBICIAK ,  Dheera Balasubramanian SAMUDRALA ,  Duc BUI

IPC: G06F9/30 ,  G06F7/78

Abstract: A method to transpose source data in a processor in response to a vector bit transpose instruction includes specifying, in respective fields of the vector bit transpose instruction, a source register containing the source data and a destination register to store transposed data. The method also includes executing the vector bit transpose instruction by interpreting N×N bits of the source data as a two-dimensional array having N rows and N columns, creating transposed source data by transposing the bits by reversing a row index and a column index for each bit, and storing the transposed source data in the destination register.

公开(公告)号：US20190243648A1

公开(公告)日：2019-08-08

申请号：US16384537

申请日：2019-04-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. ANDERSON ,  Joseph ZBICIAK ,  Duc BUI ,  Mel Alan PHIPPS ,  Todd T. HAHN

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F11/00

CPC classification number: G06F9/3016 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3822 ,  G06F9/383 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/10 ,  G06F11/1048 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/452 ,  G06F2212/60

Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, wherein the instruction execution pipeline is in a first execution mode, beginning execution of the first instruction on the instruction execution pipeline, receiving an execution mode instruction to switch the instruction execution pipeline to a second execution mode, switching the instruction execution pipeline to the second execution mode based on the received execution mode instruction, annulling the first instruction based on the execution mode instruction, receiving a second instruction for execution on the instruction execution pipeline, the second instruction, and executing the second instruction.

公开(公告)号：US20240028338A1

公开(公告)日：2024-01-25

申请号：US18479165

申请日：2023-10-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Duc BUI ,  Rama VENKATASUBRAMANIAN ,  Dheera Balasubramanian SAMUDRALA ,  Alan DAVIS

IPC: G06F9/30 ,  G11C11/409 ,  G06F12/02 ,  G06F9/38 ,  G06F16/31 ,  G06F16/901 ,  G06F16/41 ,  G06F9/445

CPC classification number: G06F9/30145 ,  G06F9/30105 ,  G11C11/409 ,  G06F12/0246 ,  G06F12/0292 ,  G06F9/30007 ,  G06F9/3001 ,  G06F9/30101 ,  G06F9/3818 ,  G06F9/30043 ,  G06F9/30032 ,  G06F16/322 ,  G06F16/9017 ,  G06F16/41 ,  G06F9/44505 ,  G06F3/0647

Abstract: A digital data processor includes an instruction memory storing instructions each specifying a data processing operation and at least one data operand field, an instruction decoder coupled to the instruction memory for sequentially recalling instructions from the instruction memory and determining the data processing operation and the at least one data operand, and at least one operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon at least one operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to increment histogram values in response to a histogram instruction by incrementing a bin entry at a specified location in a specified number of at least one histogram.

公开(公告)号：US20220413863A1

公开(公告)日：2022-12-29

申请号：US17901940

申请日：2022-09-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Duc BUI ,  Dheera Balasubramanian SAMUDRALA ,  Rama VENKATASUBRAMANIAN

IPC: G06F9/30 ,  G06F16/31 ,  G06F9/38 ,  G06F9/445 ,  G06F12/02 ,  G06F16/901 ,  G06F16/41 ,  G11C11/409 ,  G06F12/0811 ,  G06F3/06 ,  G06F9/355

Abstract: A digital data processor includes a multi-stage butterfly network, which is configured to, in response to a look up table read instruction, receive look up table data from an intermediate register, reorder the look up table data based on control signals comprising look up table configuration register data, and write the reordered look up table data to a destination register specified by the look up table read instruction.

公开(公告)号：US20200371796A1

公开(公告)日：2020-11-26

申请号：US16422795

申请日：2019-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. ANDERSON ,  Duc BUI

IPC: G06F9/30

Abstract: A method to reverse source data in a processor in response to a vector reverse instruction includes specifying, in respective fields of the vector reverse instruction, a source register containing the source data and a destination register. The source register includes a plurality of lanes and each lane contains a data element, and the destination register includes a plurality of lanes corresponding to the lanes of the source register. The method further includes executing the vector reverse instruction by creating reversed source data by reversing the order of the data elements, and storing the reversed source data in the destination register.

公开(公告)号：US20190266013A1

公开(公告)日：2019-08-29

申请号：US16384484

申请日：2019-04-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Duc BUI ,  Timothy D. ANDERSON

IPC: G06F9/48 ,  G06F9/38

Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, wherein the instruction execution pipeline is in a first execution mode, and wherein the first instruction is configured to utilize a first memory location, begin execution of the first instruction on the instruction execution pipeline, receiving an execution mode instruction to switch the instruction execution pipeline to a second execution mode, switching the instruction execution pipeline to the second execution mode based on the received execution mode instruction, receiving a second instruction for execution on the instruction execution pipeline, the second instruction configured to utilize the first memory location, determining that the first instruction and the second instruction utilize the first memory location, and stalling execution of the second instruction based on the determining.

公开(公告)号：US20240036876A1

公开(公告)日：2024-02-01

申请号：US18487186

申请日：2023-10-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. ANDERSON ,  Duc BUI ,  Joseph ZBICIAK ,  Reid E. TATGE

IPC: G06F9/38

CPC classification number: G06F9/3867 ,  G06F9/3838

Abstract: Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor. The method comprises detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.

公开(公告)号：US20240036867A1

公开(公告)日：2024-02-01

申请号：US18378207

申请日：2023-10-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Kai CHIRCA ,  Timothy D. ANDERSON ,  Duc BUI ,  Abhijeet A. CHACHAD ,  Son Hung TRAN

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/00 ,  G06F12/0897 ,  G06F12/0875 ,  G06F9/32 ,  G06F11/10 ,  G06F9/345

CPC classification number: G06F9/3016 ,  G06F9/3802 ,  G06F9/30014 ,  G06F9/30145 ,  G06F9/30036 ,  G06F9/3867 ,  G06F11/00 ,  G06F12/0897 ,  G06F12/0875 ,  G06F9/32 ,  G06F9/30098 ,  G06F11/1048 ,  G06F9/383 ,  G06F9/30112 ,  G06F9/345 ,  G06F9/30043 ,  G06F9/3834 ,  G06F9/3877 ,  G06F9/30101 ,  G06F9/3822 ,  G06F11/10 ,  G06F2212/60 ,  G06F2212/452 ,  G06F12/0811

Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction configured to cause the processor to output a first data value to a first address in a first data cache, outputting, by the processor, the first data value to a second address in a second data cache, receiving a second instruction configured to cause a streaming engine associated with the processor to prefetch data from the first data cache, determining that the first data value has not been outputted from the second data cache to the first data cache, stalling execution of the second instruction, receiving an indication, from the second data cache, that the first data value has been output from the second data cache to the first data cache, and resuming execution of the second instruction based on the received indication.

公开(公告)号：US20210294639A1

公开(公告)日：2021-09-23

申请号：US17340211

申请日：2021-06-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Duc BUI ,  Timothy D. ANDERSON

IPC: G06F9/48 ,  G06F9/38

Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, wherein the instruction execution pipeline is in a first execution mode, and wherein the first instruction is configured to utilize a first memory location, begin execution of the first instruction on the instruction execution pipeline, receiving an execution mode instruction to switch the instruction execution pipeline to a second execution mode, switching the instruction execution pipeline to the second execution mode based on the received execution mode instruction, receiving a second instruction for execution on the instruction execution pipeline, the second instruction configured to utilize the first memory location, determining that the first instruction and the second instruction utilize the first memory location, and stalling execution of the second instruction based on the determining.