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公开(公告)号：US20160165536A1
公开(公告)日：2016-06-09
申请号：US14560011
申请日：2014-12-04
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriram Murali , Sarma Gunturi , Jaiganesh Balakrishnan , Murugesh Subramaniam , Harikrishna Parthasarathy
CPC classification number: H04W52/028 , H04B1/44 , H04L5/16 , H04L25/4902 , H04L27/14 , H04W76/28 , Y02D70/1262 , Y02D70/142 , Y02D70/168
Abstract: Circuits and methods for reducing power consumption in a half-duplex transceiver are disclosed. In an embodiment, a power management circuit of half-duplex transceiver includes direct current to direct current (DC-DC) converter and snooze mode controller. The DC-DC converter includes switching circuit and driver circuit to drive the switching circuit. The DC-DC converter provides power supply to at least one element of a transmitter sub-system of the half-duplex transceiver, and operates in snooze control modes. The snooze mode controller is coupled to the DC-DC converter and configured to generate a control signal based on at least one transceiver operating input, where the control signal causes the DC-DC converter to operate in one of the snooze control modes, the snooze control modes corresponding to snooze duty cycles and where in each snooze control mode, the switching circuit and the driver circuit remain in an OFF-state based on a respective snooze duty cycle.
Abstract translation: 公开了一种用于降低半双工收发器功耗的电路和方法。 在一个实施例中，半双工收发器的功率管理电路包括直流到直流（DC-DC）转换器和打盹模式控制器。 DC-DC转换器包括开关电路和驱动电路来驱动开关电路。 DC-DC转换器为半双工收发器的发射机子系统的至少一个元件提供电源，并且以贪睡控制模式操作。 打盹模式控制器耦合到DC-DC转换器，并被配置为基于至少一个收发器操作输入产生控制信号，其中控制信号使DC-DC转换器以打盹控制模式之一进行操作，打盹 对应于打盹占空比的控制模式，并且在每个打盹控制模式中，基于相应的打盹占空比，开关电路和驱动电路保持在OFF状态。
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公开(公告)号：US11824508B2
公开(公告)日：2023-11-21
申请号：US17465243
申请日：2021-09-02
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Harikrishna Parthasarathy , Arnab Das
IPC: H03G3/30
CPC classification number: H03G3/3057
Abstract: An integrated circuit device is provided. In some examples, the integrated circuit device includes an amplifier stage that receives an input signal and a control signal and provides an amplified signal in response. A main path is coupled to the amplifier stage that receives the amplified signal and provides a first feedback signal corresponding to a signal strength of a data-bearing portion of the input signal. A control path also receives the amplified signal and provides a second feedback signal corresponding to a signal strength of the data-bearing portion and an interference component. A gain control circuit is coupled to the main path and the control path that receives the first and second feedback signals and provides the control signal in response to the feedback signals. In some such examples, the control path and main path include separate mixer stages with different performance characteristics.
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公开(公告)号：US11158936B2
公开(公告)日：2021-10-26
申请号：US16428471
申请日：2019-05-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Harikrishna Parthasarathy
Abstract: A half-duplex transceiver includes an antenna, antenna-side transformer windings coupled to the antenna, and a low-noise amplifier coupled to the antenna by the antenna-side transformer windings.
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公开(公告)号：US12063019B2
公开(公告)日：2024-08-13
申请号：US18487573
申请日：2023-10-16
Applicant: Texas Instruments Incorporated
Inventor： Harikrishna Parthasarathy , Arnab Das
IPC: H03G3/30
CPC classification number: H03G3/3057
Abstract: An integrated circuit device is provided. In some examples, the integrated circuit device includes an amplifier stage that receives an input signal and a control signal and provides an amplified signal in response. A main path is coupled to the amplifier stage that receives the amplified signal and provides a first feedback signal corresponding to a signal strength of a data-bearing portion of the input signal. A control path also receives the amplified signal and provides a second feedback signal corresponding to a signal strength of the data-bearing portion and an interference component. A gain control circuit is coupled to the main path and the control path that receives the first and second feedback signals and provides the control signal in response to the feedback signals. In some such examples, the control path and main path include separate mixer stages with different performance characteristics.
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公开(公告)号：US20210399706A1
公开(公告)日：2021-12-23
申请号：US17465243
申请日：2021-09-02
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Harikrishna Parthasarathy , Arnab Das
IPC: H03G3/30
Abstract: An integrated circuit device is provided. In some examples, the integrated circuit device includes an amplifier stage that receives an input signal and a control signal and provides an amplified signal in response. A main path is coupled to the amplifier stage that receives the amplified signal and provides a first feedback signal corresponding to a signal strength of a data-bearing portion of the input signal. A control path also receives the amplified signal and provides a second feedback signal corresponding to a signal strength of the data-bearing portion and an interference component. A gain control circuit is coupled to the main path and the control path that receives the first and second feedback signals and provides the control signal in response to the feedback signals. In some such examples, the control path and main path include separate mixer stages with different performance characteristics.
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Patent Agency Ranking
6.发明授权Switch pairs between resistor network and high/low DC converter comparator input 有权电阻网络与高/低直流转换器比较器输入之间的开关对公开(公告)号：US09048728B2
公开(公告)日：2015-06-02
申请号：US13647156
申请日：2012-10-08
Applicant: Texas Instruments Incorporated
Inventor： Harikrishna Parthasarathy , Srinivas Venkata Veeramreddi , Sudhir Polarouthu , Baher S. Haroun
CPC classification number: H02M3/1563
Abstract: Two hysteresis levels, a high level and a low level, may be used to set a period (and the switching frequency) of the output voltage of a DC-DC converter, as well as the output ripple of the converter. These two thresholds may be changed using pairs of switches. By controlling the sequence and the duration of the on-time of the switches, spectral spurs in the output can be controlled and the amplitude and the frequency band of interest can be reduced. Additional spur reduction may be possible by randomizing the control of the switches.
Abstract translation: 可以使用两个滞后电平（高电平和低电平）来设置DC-DC转换器的输出电压的周期（和开关频率）以及转换器的输出纹波。 这两个阈值可以使用成对的开关来改变。 通过控制开关的导通时间的顺序和持续时间，可以控制输出中的频谱杂散，并且可以减小感兴趣的幅度和频带。 通过对开关的控制进行随机化，可以实现额外的齿间减少。
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公开(公告)号：US20250004492A1
公开(公告)日：2025-01-02
申请号：US18217388
申请日：2023-06-30
Applicant: Texas Instruments Incorporated
Inventor： Harikrishna Parthasarathy , Khyati Bansal , Venkatesh Kadlimatti , Kunal Karanjkar
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed corresponding to a voltage regulator. An example circuit includes an output terminal; a first transistor including a current terminal and a control terminal coupled to an output terminal; a second transistor including a control terminal and a current terminal coupled to the control terminal of the first transistor; a third transistor including a first current terminal and a second current terminal, the first current terminal of the third transistor coupled to the output terminal; current mirror circuitry including a terminal coupled to the second current terminal of the third transistor; and inverter circuitry including an input terminal and an output terminal, the input terminal coupled to the terminal of the current mirror and the second current terminal of the third transistor, the output terminal coupled to the control terminal of the second transistor.
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公开(公告)号：US20240056047A1
公开(公告)日：2024-02-15
申请号：US18487573
申请日：2023-10-16
Applicant: Texas Instruments Incorporated
Inventor： Harikrishna Parthasarathy , Arnab Das
IPC: H03G3/30
CPC classification number: H03G3/3057
Abstract: An integrated circuit device is provided. In some examples, the integrated circuit device includes an amplifier stage that receives an input signal and a control signal and provides an amplified signal in response. A main path is coupled to the amplifier stage that receives the amplified signal and provides a first feedback signal corresponding to a signal strength of a data-bearing portion of the input signal. A control path also receives the amplified signal and provides a second feedback signal corresponding to a signal strength of the data-bearing portion and an interference component. A gain control circuit is coupled to the main path and the control path that receives the first and second feedback signals and provides the control signal in response to the feedback signals. In some such examples, the control path and main path include separate mixer stages with different performance characteristics.
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公开(公告)号：US20210083639A1
公开(公告)日：2021-03-18
申请号：US16575132
申请日：2019-09-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Harikrishna Parthasarathy , Arnab Das
IPC: H03G3/30
Abstract: An integrated circuit device is provided. In some examples, the integrated circuit device includes an amplifier stage that receives an input signal and a control signal and provides an amplified signal in response. A main path is coupled to the amplifier stage that receives the amplified signal and provides a first feedback signal corresponding to a signal strength of a data-bearing portion of the input signal. A control path also receives the amplified signal and provides a second feedback signal corresponding to a signal strength of the data-bearing portion and an interference component. A gain control circuit is coupled to the main path and the control path that receives the first and second feedback signals and provides the control signal in response to the feedback signals. In some such examples, the control path and main path include separate mixer stages with different performance characteristics.
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公开(公告)号：US20250103077A1
公开(公告)日：2025-03-27
申请号：US18371537
申请日：2023-09-22
Applicant: Texas Instruments Incorporated
Inventor： Rinu Mathew , Venkatesh Kadlimatti , Harikrishna Parthasarathy
Abstract: A power supply system may include multiple DC-to-DC (direct current) voltage regulators coupled in parallel to a load, and control circuitry to control the parallel-operating regulators. The control circuitry may include a first share control circuit, a second share control circuit, and a voltage regulation circuit. The first and second share control circuits may operate together with the voltage regulation circuit to control, respectively, the parallel-operating regulators to regulate a common output voltage. Additionally, first and second share control circuits may operate together with the voltage regulation circuit to control respective share of the load current by the parallel-operating regulators.
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