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公开(公告)号：US11101726B2
公开(公告)日：2021-08-24
申请号：US16589799
申请日：2019-10-01
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Subhash Sahni , Murugesh Subramaniam , Pranav Sinha
Abstract: A circuit includes a first gate control circuit including a first time delay element and first and second logic gates. The first time delay element and first and second logic gates receive a pulse width modulation (PWM) signal. The first logic gate includes a first output and second logic gate includes a second output. The circuit also includes a second gate control circuit that includes a second time delay element and third and fourth logic gates. The second time delay element includes an input coupled to the output of the first time delay element. The third logic gate includes a third output, and the fourth logic gate includes a fourth output. A first gate driver receives a first signal from one of the first or third outputs. A second gate driver receives a second signal from one of the second or fourth outputs.
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公开(公告)号：US09756572B2
公开(公告)日：2017-09-05
申请号：US14560011
申请日：2014-12-04
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriram Murali , Sarma Gunturi , Jaiganesh Balakrishnan , Murugesh Subramaniam , Harikrishna Parthasarathy
CPC classification number: H04W52/028 , H04B1/44 , H04L5/16 , H04L25/4902 , H04L27/14 , H04W76/28 , Y02D70/1262 , Y02D70/142 , Y02D70/168
Abstract: Circuits and methods for reducing power consumption in a half-duplex transceiver are disclosed. In an embodiment, a power management circuit of half-duplex transceiver includes direct current to direct current (DC-DC) converter and snooze mode controller. The DC-DC converter includes switching circuit and driver circuit to drive the switching circuit. The DC-DC converter provides power supply to at least one element of a transmitter sub-system of the half-duplex transceiver, and operates in snooze control modes. The snooze mode controller is coupled to the DC-DC converter and configured to generate a control signal based on at least one transceiver operating input, where the control signal causes the DC-DC converter to operate in one of the snooze control modes, the snooze control modes corresponding to snooze duty cycles and where in each snooze control mode, the switching circuit and the driver circuit remain in an OFF-state based on a respective snooze duty cycle.
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公开(公告)号：US20160165536A1
公开(公告)日：2016-06-09
申请号：US14560011
申请日：2014-12-04
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriram Murali , Sarma Gunturi , Jaiganesh Balakrishnan , Murugesh Subramaniam , Harikrishna Parthasarathy
CPC classification number: H04W52/028 , H04B1/44 , H04L5/16 , H04L25/4902 , H04L27/14 , H04W76/28 , Y02D70/1262 , Y02D70/142 , Y02D70/168
Abstract: Circuits and methods for reducing power consumption in a half-duplex transceiver are disclosed. In an embodiment, a power management circuit of half-duplex transceiver includes direct current to direct current (DC-DC) converter and snooze mode controller. The DC-DC converter includes switching circuit and driver circuit to drive the switching circuit. The DC-DC converter provides power supply to at least one element of a transmitter sub-system of the half-duplex transceiver, and operates in snooze control modes. The snooze mode controller is coupled to the DC-DC converter and configured to generate a control signal based on at least one transceiver operating input, where the control signal causes the DC-DC converter to operate in one of the snooze control modes, the snooze control modes corresponding to snooze duty cycles and where in each snooze control mode, the switching circuit and the driver circuit remain in an OFF-state based on a respective snooze duty cycle.
Abstract translation: 公开了一种用于降低半双工收发器功耗的电路和方法。 在一个实施例中，半双工收发器的功率管理电路包括直流到直流（DC-DC）转换器和打盹模式控制器。 DC-DC转换器包括开关电路和驱动电路来驱动开关电路。 DC-DC转换器为半双工收发器的发射机子系统的至少一个元件提供电源，并且以贪睡控制模式操作。 打盹模式控制器耦合到DC-DC转换器，并被配置为基于至少一个收发器操作输入产生控制信号，其中控制信号使DC-DC转换器以打盹控制模式之一进行操作，打盹 对应于打盹占空比的控制模式，并且在每个打盹控制模式中，基于相应的打盹占空比，开关电路和驱动电路保持在OFF状态。
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公开(公告)号：US11817772B2
公开(公告)日：2023-11-14
申请号：US17380135
申请日：2021-07-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Subhash Sahni , Murugesh Subramaniam , Pranav Sinha
CPC classification number: H02M1/08 , H02M1/38 , H02M3/157 , H02M3/158 , H03K17/08 , H03K17/284 , H03K19/20 , H03K2017/0806
Abstract: A circuit includes a first gate control circuit including a first time delay element and first and second logic gates. The first time delay element and first and second logic gates receive a pulse width modulation (PWM) signal. The first logic gate includes a first output and second logic gate includes a second output. The circuit also includes a second gate control circuit that includes a second time delay element and third and fourth logic gates. The second time delay element includes an input coupled to the output of the first time delay element. The third logic gate includes a third output, and the fourth logic gate includes a fourth output. A first gate driver receives a first signal from one of the first or third outputs. A second gate driver receives a second signal from one of the second or fourth outputs.
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