公开(公告)号：US10691074B2

公开(公告)日：2020-06-23

申请号：US16403774

申请日：2019-05-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Yao ,  Sinjeet Dhanvantray Parekh

IPC: G04F10/00 ,  H03L7/197

Abstract: A time-to-digital converter circuit includes a logic gate coupled to receive a first trigger signal indicative of a first clock signal and a second trigger signal indicative of a second clock signal. The logic gate is to generate a logic gate output signal responsive to the earlier of the first or second trigger signals to be a logic high. A synchronization circuit is included and is coupled to the logic gate and is configured to synchronize the logic gate output signal to a third clock to produce a synchronization output signal. A counter circuit counts pulses of the synchronization output signal.

公开(公告)号：US10516401B2

公开(公告)日：2019-12-24

申请号：US16214179

申请日：2018-12-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jayawardan Janardhanan ,  Eric Paul Lindgren ,  Henry Yao

IPC: H03L7/081 ,  H03L7/10

Abstract: A circuit includes a time-to-digital converter (TDC) to produce an output signal that is a function of a time difference between a first input clock to the TDC and a second input clock to the TDC. A first delay line is also included to add a time delay to a third clock to produce the first input clock. A pseudo random binary sequence generator generates a pseudo random binary bit sequence to be used to vary the amount of time delay added by the first delay line to the third clock.