公开(公告)号：US20210255869A1

公开(公告)日：2021-08-19

申请号：US17306350

申请日：2021-05-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jayasree Sankaranarayanan ,  Dipan Kumar Mandal

IPC: G06F9/38 ,  G06F9/30

Abstract: This disclosure is directed to the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD processor. The invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. This enables data processing by vector single instruction multiple data (SIMD) operations. This vector destination register load can be repeated if the tables store more used data. New data can be loaded into the original tables if appropriate. A level one memory is preferably partitioned as part data cache and part directly addressable memory. The look up table memory is stored in the directly addressable memory.

公开(公告)号：US20170076173A1

公开(公告)日：2017-03-16

申请号：US15345523

申请日：2016-11-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jayasree Sankaranarayanan ,  Dipan Kumar Mandal ,  Prashanth R. Viswanath

IPC: G06K9/46 ,  G06K9/62 ,  G06K9/00 ,  G06K9/48

CPC classification number: G06K9/4638 ,  G06K9/00986 ,  G06K9/4604 ,  G06K9/481 ,  G06K9/6211

Abstract: This invention enables effective corner detection of pixels of an image using the FAST algorithm using a vector SIMD processor. This invention loads an 8×8 pixel block that includes four 7×7 pixel blocks including the 16 peripheral pixels to be tested for each of four center pixels. This invention rearranges the 64 pixels of the 8×8 block to form a 16 element array for each center pixel preferably using a vector permutation instruction. This invention uses vector SIMD subtraction and compare and vector SIMD addition and compare to make the FAST algorithm comparisons. The N consecutive pixels determinations of the FAST algorithm are made from the results of plural shift and AND operations. The corresponding center pixel is marked a corner or not a corner dependent upon of the results of plural shift and AND operations.

Abstract translation: 本发明可以使用使用向量SIMD处理器的FAST算法来有效地角度检测图像的像素。 本发明加载包括四个7×7像素块的8×8像素块，包括要测试的四个中心像素中的每一个的16个外围像素。 本发明重新排列8×8块的64个像素，优选地使用向量置换指令来为每个中心像素形成16个元件阵列。 本发明使用矢量SIMD减法和比较和矢量SIMD加法比较，使得FAST算法比较。 FAST算法的N个连续像素确定由多个移位和“与”运算的结果进行。 取决于多个换档和“与”运算的结果，相应的中心像素被标记为拐角或不标记角。

公开(公告)号：US20160125257A1

公开(公告)日：2016-05-05

申请号：US14581401

申请日：2014-12-23

Applicant: Texas Instruments Incorporated

Inventor： Jayasree Sankaranarayanan ,  Dipan Kumar Mandal ,  Prashanth R. Viswanath

IPC: G06K9/46 ,  G06K9/62

CPC classification number: G06K9/4638 ,  G06K9/00986 ,  G06K9/4604 ,  G06K9/481 ,  G06K9/6211

Abstract: This invention enables effective corner detection of pixels of an image using the FAST algorithm using a vector SIMD processor. This invention loads an 8×8 pixel block that includes four 7×7 pixel blocks including the 16 peripheral pixels to be tested for each of four center pixels. This invention rearranges the 64 pixels of the 8×8 block to form a 16 element array for each center pixel preferably using a vector permutation instruction. This invention uses vector SIMD subtraction and compare and vector SIMD addition and compare to make the FAST algorithm comparisons. The N consecutive pixels determinations of the FAST algorithm are made from the results of plural shift and AND operations. The corresponding center pixel is marked a corner or not a corner dependent upon of the results of plural shift and AND operations.

Abstract translation: 本发明可以使用使用向量SIMD处理器的FAST算法来有效地角度检测图像的像素。 本发明加载包括四个7×7像素块的8×8像素块，包括要测试的四个中心像素中的每一个的16个外围像素。 本发明重新排列8×8块的64个像素，优选地使用向量置换指令来为每个中心像素形成16个元件阵列。 本发明使用矢量SIMD减法和比较和矢量SIMD加法比较，使得FAST算法比较。 FAST算法的N个连续像素确定由多个移位和“与”运算的结果进行。 取决于多个换档和“与”运算的结果，相应的中心像素被标记为拐角或不标记角。

公开(公告)号：US10996955B2

公开(公告)日：2021-05-04

申请号：US16451330

申请日：2019-06-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jayasree Sankaranarayanan ,  Dipan Kumar Mandal

IPC: G06F9/38 ,  G06F9/30

Abstract: This disclosure is directed to the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD processor. The invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. This enables data processing by vector single instruction multiple data (SIMD) operations. This vector destination register load can be repeated if the tables store more used data. New data can be loaded into the original tables if appropriate. A level one memory is preferably partitioned as part data cache and part directly addressable memory. The look up table memory is stored in the directly addressable memory.

公开(公告)号：US10331347B2

公开(公告)日：2019-06-25

申请号：US15991653

申请日：2018-05-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jayasree Sankaranarayanan ,  Dipan Kumar Mandal

IPC: G06F3/06 ,  G06F9/30 ,  G06F9/38

Abstract: This disclosure is directed to the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD processor. The invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. This enables data processing by vector single instruction multiple data (SIMD) operations. This vector destination register load can be repeated if the tables store more used data. New data can be loaded into the original tables if appropriate. A level one memory is preferably partitioned as part data cache and part directly addressable memory. The look up table memory is stored in the directly addressable memory.

公开(公告)号：US09652686B2

公开(公告)日：2017-05-16

申请号：US15345523

申请日：2016-11-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jayasree Sankaranarayanan ,  Dipan Kumar Mandal ,  Prashanth R Viswanath

IPC: G06K9/46 ,  G06K9/48 ,  G06K9/62 ,  G06K9/00

CPC classification number: G06K9/4638 ,  G06K9/00986 ,  G06K9/4604 ,  G06K9/481 ,  G06K9/6211

Abstract: This invention enables effective corner detection of pixels of an image using the FAST algorithm using a vector SIMD processor. This invention loads an 8×8 pixel block that includes four 7×7 pixel blocks including the 16 peripheral pixels to be tested for each of four center pixels. This invention rearranges the 64 pixels of the 8×8 block to form a 16 element array for each center pixel preferably using a vector permutation instruction. This invention uses vector SIMD subtraction and compare and vector SIMD addition and compare to make the FAST algorithm comparisons. The N consecutive pixels determinations of the FAST algorithm are made from the results of plural shift and AND operations. The corresponding center pixel is marked a corner or not a corner dependent upon of the results of plural shift and AND operations.

公开(公告)号：US12056491B2

公开(公告)日：2024-08-06

申请号：US18321037

申请日：2023-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jayasree Sankaranarayanan ,  Dipan Kumar Mandal

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/383 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043

Abstract: This disclosure is directed to the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD processor. The invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. This enables data processing by vector single instruction multiple data (SIMD) operations. This vector destination register load can be repeated if the tables store more used data. New data can be loaded into the original tables if appropriate. A level one memory is preferably partitioned as part data cache and part directly addressable memory. The look up table memory is stored in the directly addressable memory.

公开(公告)号：US10395381B2

公开(公告)日：2019-08-27

申请号：US16291405

申请日：2019-03-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jayasree Sankaranarayanan ,  Dipan Kumar Mandal

IPC: G06T7/60 ,  G06F9/38 ,  G06F9/30 ,  G06T1/20 ,  G06F17/16

Abstract: Disclosed techniques relate to forming a block sum of picture elements employing a vector dot product instruction to sum packed picture elements and the mask producing a vector of masked horizontal picture element. The block sum is formed from plural horizontal sums via vector single instruction multiple data (SIMD) addition.

公开(公告)号：US20190197718A1

公开(公告)日：2019-06-27

申请号：US16291405

申请日：2019-03-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jayasree Sankaranarayanan ,  Dipan Kumar Mandal

IPC: G06T7/60 ,  G06F9/38 ,  G06F9/30 ,  G06T1/20 ,  G06F17/16

CPC classification number: G06T7/60 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/3887 ,  G06F9/3891 ,  G06F17/16 ,  G06T1/20 ,  G06T2200/28

Abstract: Disclosed techniques relate to forming a block sum of picture elements employing a vector dot product instruction to sum packed picture elements and the mask producing a vector of masked horizontal picture element. The block sum is formed from plural horizontal sums via vector single instruction multiple data (SIMD) addition.

公开(公告)号：US20160124651A1

公开(公告)日：2016-05-05

申请号：US14920365

申请日：2015-10-22

Applicant: Texas Instruments Incorporated

Inventor： Jayasree Sankaranarayanan ,  Dipan Kumar Mandal

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F9/383 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043

Abstract: This invention deals with the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD processor. The invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. This enables data processing by vector single instruction multiple data (SIMD) operations. This vector destination register load can be repeated if the tables store more used data. New data can be loaded into the original tables if appropriate. A level one memory is preferably partitioned as part data cache and part directly addressable memory. The look up table memory is stored in the directly addressable memory.

Abstract translation: 本发明涉及在用于向量SIMD处理器的合理大小的数据块内并行随机读取访问的问题。 本发明设置多个并行查找表，将数据从主存储器移动到每个多个并行查找表，然后使用查找表读取指令来同时将数据从每个并行查找表移动到相应部分的向量目标寄存器。 这使得能够通过矢量单指令多数据（SIMD）操作进行数据处理。 如果表存储更多使用的数据，则可以重复此向量目标寄存器加载。 如果适用，新数据可以加载到原始表中。 一级存储器优选地被分割为部分数据高速缓存和部分直接可寻址存储器。 查找表存储器存储在可直接寻址的存储器中。