公开(公告)号：US20230307557A1

公开(公告)日：2023-09-28

申请号：US17665497

申请日：2022-02-05

Applicant: Texas Instruments Incorporated

Inventor： Honglin Guo ,  Zachary K Lee ,  Jingjing Chen

IPC: H01L29/94 ,  H01L29/66

CPC classification number: H01L29/94 ,  H01L29/66189 ,  H01L21/26513

Abstract: An integrated circuit includes an SOI substrate having a semiconductor layer over a buried insulator layer; the semiconductor layer contains white space regions that include a PWELL region. An electronic device includes an NWELL region in the semiconductor layer, a dielectric over the NWELL region, and a polysilicon plate over the dielectric. A sacrificial NWELL ring is adjacent to and separated from the NWELL region by a first gap.

公开(公告)号：US20230253495A1

公开(公告)日：2023-08-10

申请号：US17665381

申请日：2022-02-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jingjing Chen ,  Ming-Yeh Chuang ,  Guruvayurappan Mathur ,  James Todd ,  Ronald Chin ,  Thomas Lillibridge

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7825 ,  H01L29/4236 ,  H01L29/41758 ,  H01L29/66515

Abstract: The present disclosure generally relates to a bird's beak profile of a field oxide region. In an example, a semiconductor device structure includes a semiconductor substrate, a dielectric oxide layer, and a field oxide region. The semiconductor substrate has a top surface. The dielectric oxide layer is over the top surface of the semiconductor substrate. The field oxide region is over the semiconductor substrate. The field oxide region is connected to the dielectric oxide layer through a bird's beak region. A lower surface of the bird's beak region interfaces with the semiconductor substrate. In a cross-section along a direction from the field oxide region to the dielectric oxide layer, the lower surface of the bird's beak region does not have a slope with a magnitude that exceeds 0.57735, where rise of the slope is in a direction normal to the top surface of the semiconductor substrate.

公开(公告)号：US20240321677A1

公开(公告)日：2024-09-26

申请号：US18397476

申请日：2023-12-27

Applicant: Texas Instruments Incorporated

Inventor： Jingjing Chen ,  Archana Venugopal

IPC: H01L23/38 ,  H01L23/532 ,  H01L29/78

CPC classification number: H01L23/38 ,  H01L23/53209 ,  H01L29/7824

Abstract: Semiconductor devices including thermoelectric coolers and method of operating the semiconductor devices are described. A semiconductor device includes an SOI substrate with one or more components (e.g., a transistor) generating heat during operation. The semiconductor device includes a thermoelectric cooler surrounding the transistor. The thermoelectric cooler includes a first electrode laterally surrounding the transistor, a holey silicon region laterally surrounding and contacting the first electrode, and a second electrode laterally surrounding and contacting the holey silicon region. The thermoelectric cooler, when activated, can reduce operating temperature of the transistor. In some cases, pre-cooling may be done to further reduce the operating temperature.

公开(公告)号：US20240178283A1

公开(公告)日：2024-05-30

申请号：US18072515

申请日：2022-11-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jingjing Chen

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/402 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/66681 ,  H01L29/7816

Abstract: An LDMOS device includes a semiconductor substrate with an epitaxial layer that comprises a body region and a drain drift region. A drain region is formed in the drain drift region and a source region is formed in the body region. A gate shield may be formed over a gate shield dielectric layer disposed over a gate electrode, the gate shield having a variable length and tied to the source that is provided with a body connection via a deep trench contact.

公开(公告)号：US20240145603A1

公开(公告)日：2024-05-02

申请号：US18408001

申请日：2024-01-09

Applicant: Texas Instruments Incorporated

Inventor： Honglin Guo ,  Zachary K. Lee ,  Jingjing Chen

IPC: H01L29/94 ,  H01L29/66

CPC classification number: H01L29/94 ,  H01L29/66189 ,  H01L21/26586

Abstract: An integrated circuit includes an SOI substrate having a semiconductor layer over a buried insulator layer; the semiconductor layer contains white space regions that include a PWELL region. An electronic device includes an NWELL region in the semiconductor layer, a dielectric over the NWELL region, and a polysilicon plate over the dielectric. A sacrificial NWELL ring is adjacent to and separated from the NWELL region by a first gap.

公开(公告)号：US20240363484A1

公开(公告)日：2024-10-31

申请号：US18308411

申请日：2023-04-27

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Jingjing Chen

IPC: H01L23/38 ,  H10N10/01 ,  H10N10/17

CPC classification number: H01L23/38 ,  H10N10/01 ,  H10N10/17

Abstract: An electronic device includes a semiconductor die with first and second sides, a semiconductor layer extending to the first side, an array of unit cells arranged in rows columns, and a conductive reference terminal in the semiconductor layer that laterally surrounds the array, the first and second sides being spaced apart from one another by a thickness distance of 50 μm or less, and the respective unit cells including: a circuit component in the semiconductor layer; a holey semiconductor portion in the semiconductor layer that laterally surrounds the respective circuit component and includes holes that extend from the metallization structure toward the first side; and a conductive control terminal in the semiconductor layer that laterally surrounds the respective holey semiconductor portion, and an adhesive layer extends between the first side of the semiconductor die and a die attach pad.

公开(公告)号：US11901462B2

公开(公告)日：2024-02-13

申请号：US17665497

申请日：2022-02-05

Applicant: Texas Instruments Incorporated

Inventor： Honglin Guo ,  Zachary K Lee ,  Jingjing Chen

IPC: H01L29/94 ,  H01L29/66 ,  H01L21/265 ,  H01L29/40 ,  H01L21/266

CPC classification number: H01L29/94 ,  H01L29/66189 ,  H01L21/266 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/401

Abstract: An integrated circuit includes an SOI substrate having a semiconductor layer over a buried insulator layer; the semiconductor layer contains white space regions that include a PWELL region. An electronic device includes an NWELL region in the semiconductor layer, a dielectric over the NWELL region, and a polysilicon plate over the dielectric. A sacrificial NWELL ring is adjacent to and separated from the NWELL region by a first gap.

公开(公告)号：US20230343828A1

公开(公告)日：2023-10-26

申请号：US17727892

申请日：2022-04-25

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Ming-Yeh Chuang ,  Jingjing Chen

IPC: H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/74 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L29/7816 ,  H01L29/1095 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/74 ,  H01L29/66681

Abstract: A method of fabricating a transistor includes forming a gate structure over a semiconductor substrate having a first conductivity type. A photoresist layer is patterned over the gate structure to remove the photoresist layer from over an uncovered portion of the gate structure and an adjacent region of the semiconductor substrate abutting the uncovered portion of the gate structure. A deep well region having the first conductivity type is formed using a first dopant such that the first dopant penetrates through the uncovered portion of the gate structure and is blocked by the photoresist layer. A shallow well region is formed by implanting a second dopant such that the second dopant penetrates the adjacent region and is blocked by the uncovered portion of the gate structure.

公开(公告)号：US20230200238A1

公开(公告)日：2023-06-22

申请号：US17836731

申请日：2022-06-09

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Jingjing Chen

IPC: H01L35/30 ,  H01L35/24 ,  H01L35/32

CPC classification number: H01L35/30 ,  H01L35/24 ,  H01L35/32

Abstract: A microelectronic device including a substrate having a semiconductor material containing an embedded thermoelectric cooler with thermally anisotropic mesas between the cold terminal and the hot terminal of the embedded thermoelectric cooler adjacent to a heat source; the adjacent embedded thermoelectric cooler providing a temperature reduction for the heat source resulting in increased safe operating area (SOA) for the microelectronic device. The thermally anisotropic mesas are formed in parallel with deep trenches used as isolation in the microelectronic device.