公开(公告)号：US20200076308A1

公开(公告)日：2020-03-05

申请号：US16292750

申请日：2019-03-05

Applicant: Texas Instruments Incorporated

Inventor： Stefan Dietrich ,  Joerg Kirchner

IPC: H02M3/158 ,  H03K17/687 ,  H03K5/24

Abstract: A current measurement linearization circuit for a DC/DC boost converter includes a back-gate sensing transistor and a back-gate reset transistor. The back-gate sensing transistor has a first terminal coupled to a first body contact of a high-side power transistor and a second terminal coupled to a second body contact of a first replica transistor in a valley-current sensing circuit. The back-gate reset transistor has a first terminal coupled to a max reference voltage that is equal to the greater of an input voltage and an output voltage and a second terminal coupled to the second body contact.

公开(公告)号：US10523116B2

公开(公告)日：2019-12-31

申请号：US16126705

申请日：2018-09-10

Applicant: Texas Instruments Incorporated

Inventor： Stefan Dietrich ,  Joerg Kirchner ,  Ruediger Ganz

IPC: H02M3/137 ,  G06F1/04 ,  H02M3/158

Abstract: A timer for creating a stable on time. The timer may have a reference voltage source, and an input voltage source. The voltage sources providing voltage that can be applied to a various circuit components such as capacitors, inductors, resistors, diodes, transistors, or other components. The reference voltage source may also be modified by a set of transistors coupled as a diode before being seen by an input of a timer comparator. The reference and input voltage source signals, which may be modified by circuit components, are compared by the timer comparator and then output as a timer control signal. The timer control signal may control a voltage converter, or the switches of a voltage converter.

公开(公告)号：US11569736B2

公开(公告)日：2023-01-31

申请号：US17184721

申请日：2021-02-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joerg Kirchner ,  Stefan Schimonsky

IPC: H02M1/36 ,  H02M1/00 ,  G05F1/575 ,  G05F1/46 ,  H02M3/157 ,  H02M3/158

Abstract: A soft-start circuit includes an error amplifier, a reference voltage ramp circuit, and a minimum current clamp circuit. The error amplifier is configured to generate a difference voltage representing a difference of a feedback voltage and a reference voltage ramp. The reference voltage ramp circuit is configured to generate the reference voltage ramp. The minimum current clamp circuit is configured to clamp an output of the error amplifier to a predetermined minimum voltage.

公开(公告)号：US10069416B2

公开(公告)日：2018-09-04

申请号：US15377075

申请日：2016-12-13

Applicant: Texas Instruments Incorporated

Inventor： Neil Gibson ,  Antonio Priego ,  Erich Bayer ,  Joerg Kirchner ,  Michael Lueders ,  Stefan Herzer ,  Michael Couleur

IPC: H02M3/158 ,  H02M1/08

CPC classification number: H02M3/158 ,  H02M1/08 ,  H02M3/1582 ,  H02M2001/0016

Abstract: A controller for a DC-DC converter includes a state machine and a plurality of drivers for controlling switches in the DC-DC converter, where each state in the state machine determines a state of the drivers, and a plurality of timers, where each state in the state machine, other than a passive state, has an associated timer for the state of the drivers.

公开(公告)号：US20250155958A1

公开(公告)日：2025-05-15

申请号：US18428220

申请日：2024-01-31

Applicant: Texas Instruments Incorporated

Inventor： Joerg Kirchner ,  Florian Neveu ,  Stefan Schimonsky

IPC: G06F1/3296

Abstract: An example apparatus includes: switching converter circuitry having an input terminal and an output terminal; and peak current control circuitry coupled to the switching converter circuitry, the peak current control circuitry including: error amplifier having an input terminal and an output terminal; power saving mode (PSM) entry circuitry having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the PSM entry circuitry coupled to the input terminal of the switching converter circuitry, the second input terminal of the PSM entry circuitry coupled to the output terminal of the switching converter circuitry and the input terminal of the error amplifier; and comparison circuitry having a first input terminal and a second input terminal, the first input terminal of the comparison circuitry coupled to the output terminal of the error amplifier.

公开(公告)号：US10651742B2

公开(公告)日：2020-05-12

申请号：US16292750

申请日：2019-03-05

Applicant: Texas Instruments Incorporated

Inventor： Stefan Dietrich ,  Joerg Kirchner

IPC: H02M3/158 ,  H03K5/24 ,  H03K17/687 ,  H02M1/00

Abstract: A current measurement linearization circuit for a DC/DC boost converter includes a back-gate sensing transistor and a back-gate reset transistor. The back-gate sensing transistor has a first terminal coupled to a first body contact of a high-side power transistor and a second terminal coupled to a second body contact of a first replica transistor in a valley-current sensing circuit. The back-gate reset transistor has a first terminal coupled to a max reference voltage that is equal to the greater of an input voltage and an output voltage and a second terminal coupled to the second body contact.

公开(公告)号：US11258363B2

公开(公告)日：2022-02-22

申请号：US16712498

申请日：2019-12-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joerg Kirchner ,  Stefan Dietrich ,  Gaetano Maria Walter Petrina

IPC: H02M3/158 ,  H02M1/00 ,  H02M1/08

Abstract: Aspects of the disclosure provide for a circuit comprising a power converter controller. In an example, the power converter controller is configured to receive a signal representative of a current of a power converter, compare the signal representative of the current of the power converter to an error signal and generate a peak current detection signal having an asserted value when the signal representative of the current of the power converter is not less than the error signal. A state machine circuit is coupled the peak current detection circuit. The state machine circuit is configured to receive the peak current detection signal, a clock signal, and a timer signal and implement a state machine to generate at least one control signal for controlling a mode and a phase of operation of the power converter based on values of the peak current detection signal, the clock signal, and the timer signal.

公开(公告)号：US20210167687A1

公开(公告)日：2021-06-03

申请号：US17176077

申请日：2021-02-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joerg Kirchner ,  Stefan Dietrich ,  Ivan Shumkov ,  Christian Harder

IPC: H02M3/158 ,  H02M1/00

Abstract: To facilitate current sensing for valley current-controlled power converters, an example apparatus includes a comparator having a first terminal, a second terminal, and an output. A first transistor has a first drain coupled to the first terminal of the comparator. A second transistor has a second drain coupled to the first terminal of the comparator. A third transistor has a third drain coupled to the second terminal of the comparator.

公开(公告)号：US10819237B1

公开(公告)日：2020-10-27

申请号：US16403999

申请日：2019-05-06

Applicant: Texas Instruments Incorporated

Inventor： Gaetano Maria Walter Petrina ,  Joerg Kirchner

IPC: H02M1/08 ,  H02M3/158 ,  H04M1/02

Abstract: A DC/DC switching converter includes high-side and low-side power NFETs coupled in series between a first pin for coupling to a first supply voltage and a second pin for coupling to a second supply voltage. A switch-node is coupled to a third pin. A first gate driver is coupled to drive a gate voltage on the high-side power NFET at a first rate and a second gate driver is coupled to drive the gate voltage of the high-side power NFET at a second rate that is higher than the first rate. A comparator is coupled to the first pin and to the gate of the high-side power NFET and further coupled to turn on the second gate driver when a gate voltage of the high-side power NFET is equal to the first supply voltage coupled to the first pin plus a threshold voltage of the high-side power NFET.

公开(公告)号：US10763748B2

公开(公告)日：2020-09-01

申请号：US15995331

申请日：2018-06-01

Applicant: Texas Instruments Incorporated

Inventor： Ivan Shumkov ,  Erich Bayer ,  Joerg Kirchner ,  Ruediger Ganz ,  Michael Lueders ,  Martin Priess ,  Nicola Rasera

IPC: H02M3/158

Abstract: Disclosed examples include inverting buck-boost DC-DC converter circuits with a switching circuit to alternate between first and second buck mode phases for buck operation in a first mode, including connecting an inductor and a capacitor in series between an input node and a reference node to charge the inductor and the capacitor in the first buck mode phase, and connecting the inductor and the capacitor in parallel between an output node and the reference node to discharge the inductor and the capacitor to the output node. For boost operation in a second mode, the switching circuit alternates between connecting the inductor and the capacitor in series between the input node and the reference node to discharge the inductor and charge the capacitor in a first boost mode phase, and connecting the inductor between the input node and the reference node to charge the inductor and connecting the capacitor between the first output node and the reference node to discharge the capacitor to deliver power to the output node in a second boost mode phase.