BOOTSTRAP CAPACITOR REFRESHING FOR INVERTING BUCK-BOOST DC-DC CONVERTERS

    公开(公告)号:US20210126538A1

    公开(公告)日:2021-04-29

    申请号:US17038410

    申请日:2020-09-30

    Abstract: A converter having an input adapted to be connected to an input voltage and an output adapted to supply an output voltage, the converter comprising: a high-side switch having a first current terminal, a second current terminal and a first control terminal, the first current terminal is coupled to the input voltage and the second current terminal is coupled to a switching node; a high-side driver circuit having an input, a first supply input, a second supply input and an output coupled to the first control terminal, the second supply input is coupled to the switching node; a bootstrap capacitor having a first terminal and a second terminal, the first terminal coupled to the first supply input and the second terminal coupled to the second supply input; a switch having a first terminal and a second terminal, the first terminal of the switch is coupled to the first terminal of the bootstrap capacitor and the second terminal of the switch is connected to a supply voltage (VDD volts above ground).

    Switched mode power supply control topology

    公开(公告)号:US11258363B2

    公开(公告)日:2022-02-22

    申请号:US16712498

    申请日:2019-12-12

    Abstract: Aspects of the disclosure provide for a circuit comprising a power converter controller. In an example, the power converter controller is configured to receive a signal representative of a current of a power converter, compare the signal representative of the current of the power converter to an error signal and generate a peak current detection signal having an asserted value when the signal representative of the current of the power converter is not less than the error signal. A state machine circuit is coupled the peak current detection circuit. The state machine circuit is configured to receive the peak current detection signal, a clock signal, and a timer signal and implement a state machine to generate at least one control signal for controlling a mode and a phase of operation of the power converter based on values of the peak current detection signal, the clock signal, and the timer signal.

    Gate voltage plateau completion circuit for DC/DC switching converters

    公开(公告)号:US10819237B1

    公开(公告)日:2020-10-27

    申请号:US16403999

    申请日:2019-05-06

    Abstract: A DC/DC switching converter includes high-side and low-side power NFETs coupled in series between a first pin for coupling to a first supply voltage and a second pin for coupling to a second supply voltage. A switch-node is coupled to a third pin. A first gate driver is coupled to drive a gate voltage on the high-side power NFET at a first rate and a second gate driver is coupled to drive the gate voltage of the high-side power NFET at a second rate that is higher than the first rate. A comparator is coupled to the first pin and to the gate of the high-side power NFET and further coupled to turn on the second gate driver when a gate voltage of the high-side power NFET is equal to the first supply voltage coupled to the first pin plus a threshold voltage of the high-side power NFET.

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