Seamless DCM-PFM transition for single pulse operation in DC-DC converters

    公开(公告)号:US11563378B2

    公开(公告)日:2023-01-24

    申请号:US17000854

    申请日:2020-08-24

    Abstract: A converter operable to convert an input voltage at an input node to an output voltage at an output node coupled to a load by switching on and off a transistor at a switching frequency, the converter comprising: an error amplifier circuit having a first input coupled to a reference voltage, a second input coupled to the output node through a resistive divider, a first output operable to output a control current and a second output operable to output a current equivalent to the control current; a peak current comparator circuit having a first input coupled to the second output of the error amplifier circuit, a second input and an output, the second input is coupled to the input node through an inductor; an off-time timer circuit having an input coupled to the first output of the error amplifier circuit and an output, the off-time timer circuit operable to set the switching frequency based on the control current; and a control circuit having a first input coupled to the output of the peak current comparator circuit, a second input coupled to the output of the off-time timer circuit and an output coupled to a control terminal of the transistor.

    Down-mode valley-current-sense replica linearization

    公开(公告)号:US10651742B2

    公开(公告)日:2020-05-12

    申请号:US16292750

    申请日:2019-03-05

    Abstract: A current measurement linearization circuit for a DC/DC boost converter includes a back-gate sensing transistor and a back-gate reset transistor. The back-gate sensing transistor has a first terminal coupled to a first body contact of a high-side power transistor and a second terminal coupled to a second body contact of a first replica transistor in a valley-current sensing circuit. The back-gate reset transistor has a first terminal coupled to a max reference voltage that is equal to the greater of an input voltage and an output voltage and a second terminal coupled to the second body contact.

    DC-DC converter with adaptive zero tracking

    公开(公告)号:US11863073B2

    公开(公告)日:2024-01-02

    申请号:US17490764

    申请日:2021-09-30

    CPC classification number: H02M3/1584 H02M1/0009 H02M1/0025 H03K3/02337

    Abstract: A DC-DC converter includes an output terminal, a reference voltage source, an error amplifier, and a compensation circuit. The error amplifier is coupled to the output terminal and the reference voltage source. The error amplifier is configured to generate an error signal representative of a difference between a voltage at the output terminal and a reference voltage provided by the reference voltage source. The compensation circuit is coupled to the error amplifier. The compensation circuit includes a resistor, a capacitor, and a switch control circuit. The resistor is coupled to the error amplifier. The capacitor is coupled to the resistor. The switch control circuit is configured to modulate connection of the resistor to the capacitor based on a switching frequency of the DC-DC converter.

    Switched-mode DC/DC converter having a bootstrapped high-side driver

    公开(公告)号:US10673337B1

    公开(公告)日:2020-06-02

    申请号:US16265027

    申请日:2019-02-01

    Abstract: A switch-node rising edge detection circuit is provided for a switched-mode DC/DC boost converter. A high-side gate-driver couples a gate of the high-side NMOS power transistor to either a first terminal of a bootstrap capacitor or the switch-node. The detection circuit includes an AND gate that receives an activation signal on a first input and provides a switching signal to the high-side gate-driver. A PMOS transistor is coupled in series with an inverter between the first terminal of the bootstrap capacitor and a second input of the AND gate. The inverter receives supply voltages from the first terminal of the bootstrap capacitor and the switch-node. The gate of the PMOS transistor receives the activation signal. An NMOS transistor is coupled between an output voltage and a node between the PMOS transistor and the inverter. A gate of the NMOS transistor is coupled to the bootstrap capacitor's first terminal.

    DOWN-MODE VALLEY-CURRENT-SENSE REPLICA LINEARIZATION

    公开(公告)号:US20200076308A1

    公开(公告)日:2020-03-05

    申请号:US16292750

    申请日:2019-03-05

    Abstract: A current measurement linearization circuit for a DC/DC boost converter includes a back-gate sensing transistor and a back-gate reset transistor. The back-gate sensing transistor has a first terminal coupled to a first body contact of a high-side power transistor and a second terminal coupled to a second body contact of a first replica transistor in a valley-current sensing circuit. The back-gate reset transistor has a first terminal coupled to a max reference voltage that is equal to the greater of an input voltage and an output voltage and a second terminal coupled to the second body contact.

    Timer for creating a stable on time

    公开(公告)号:US10523116B2

    公开(公告)日:2019-12-31

    申请号:US16126705

    申请日:2018-09-10

    Abstract: A timer for creating a stable on time. The timer may have a reference voltage source, and an input voltage source. The voltage sources providing voltage that can be applied to a various circuit components such as capacitors, inductors, resistors, diodes, transistors, or other components. The reference voltage source may also be modified by a set of transistors coupled as a diode before being seen by an input of a timer comparator. The reference and input voltage source signals, which may be modified by circuit components, are compared by the timer comparator and then output as a timer control signal. The timer control signal may control a voltage converter, or the switches of a voltage converter.

    Switched mode power supply control topology

    公开(公告)号:US11258363B2

    公开(公告)日:2022-02-22

    申请号:US16712498

    申请日:2019-12-12

    Abstract: Aspects of the disclosure provide for a circuit comprising a power converter controller. In an example, the power converter controller is configured to receive a signal representative of a current of a power converter, compare the signal representative of the current of the power converter to an error signal and generate a peak current detection signal having an asserted value when the signal representative of the current of the power converter is not less than the error signal. A state machine circuit is coupled the peak current detection circuit. The state machine circuit is configured to receive the peak current detection signal, a clock signal, and a timer signal and implement a state machine to generate at least one control signal for controlling a mode and a phase of operation of the power converter based on values of the peak current detection signal, the clock signal, and the timer signal.

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