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公开(公告)号：US11121206B2
公开(公告)日：2021-09-14
申请号：US16692349
申请日：2019-11-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Basant Bothra , Lokesh Kumar Gupta
Abstract: An electrical device includes an integrated circuit having device circuitry, a passive breakdown protection circuit, and a resistor coupled to or included with the device circuitry. The resistor includes: a polysilicon layer coupled between a first terminal and a second terminal; an epitaxial layer terminal; and a buried layer terminal. The passive breakdown protection circuit is coupled between the second terminal and the epitaxial layer terminal. The passive breakdown protection circuit is also coupled between the epitaxial layer terminal and the buried layer terminal.
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公开(公告)号：US11101794B2
公开(公告)日：2021-08-24
申请号：US16889939
申请日：2020-06-02
Applicant: Texas Instruments Incorporated
Inventor： Deep Banerjee , Lokesh Kumar Gupta , Somshubhra Paul
IPC: H04L12/40 , G05F3/26 , H03K17/16 , H03K17/30 , H03K17/687
Abstract: A driver includes an open drain output transistor, a capacitor, a first current source, and first and second transistors. Upon assertion of a transmit signal to turn on the first transistor, a controller asserts a second control signal to turn on the second transistor responsive to a voltage of the capacitor being less than a threshold voltage of the open drain output transistor to thereby increase the control terminal voltage for the open drain output transistor at a first time rate. The controller deasserts the second control signal to turn off the second transistor responsive to the capacitor voltage exceeding the threshold voltage. Responsive to the capacitor's voltage exceeding the threshold, the first current source charges the capacitor to further increase the control terminal voltage at a second time rate that is smaller than the first time rate.
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3.发明公开公开(公告)号：US20230353185A1
公开(公告)日：2023-11-02
申请号：US17730451
申请日：2022-04-27
Applicant: Texas Instruments Incorporated
Inventor： Deep Banerjee , Lokesh Kumar Gupta , Madhulatha Bonu , Vikas Thawani
CPC classification number: H04B1/405 , H04B1/44 , H04B1/0458 , H04B2001/0408
Abstract: A controller area network including one or more first network nodes biased from a first power supply voltage, and a second network node biased from a second, lower, power supply voltage. The second network node includes a transmitter driving a differential voltage onto bus lines to communicate a dominant bus state at a second dominant state common mode voltage, a receiver coupled to the bus lines, sense circuitry to sense a common mode voltage at the bus lines, and control circuitry to control a recessive state common mode voltage in response to the sensed dominant state common mode voltage.
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公开(公告)号：US20190131967A1
公开(公告)日：2019-05-02
申请号：US15834599
申请日：2017-12-07
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Deep Banerjee , Lokesh Kumar Gupta , Somshubhra Paul
IPC: H03K17/687 , G05F3/26
CPC classification number: H03K17/6871 , G05F3/262 , H03K17/163 , H03K17/302 , H04L12/4013 , H04L2012/40234
Abstract: A driver includes an open drain output transistor, a capacitor, a first current source, and first and second transistors. Upon assertion of a transmit signal to turn on the first transistor, a controller asserts a second control signal to turn on the second transistor responsive to a voltage of the capacitor being less than a threshold voltage of the open drain output transistor to thereby increase the gate voltage for the open drain output transistor at a first time rate. The controller deasserts the second control signal to turn off the second transistor responsive to the capacitor voltage exceeding the threshold voltage. Responsive to the capacitor's voltage exceeding the threshold, the first current source charges the capacitor to further increase the gate voltage at a second time rate that is smaller than the first time rate.
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5.发明授权公开(公告)号：US12255680B2
公开(公告)日：2025-03-18
申请号：US17730451
申请日：2022-04-27
Applicant: Texas Instruments Incorporated
Inventor： Deep Banerjee , Lokesh Kumar Gupta , Madhulatha Bonu , Vikas Thawani
Abstract: A controller area network including one or more first network nodes biased from a first power supply voltage, and a second network node biased from a second, lower, power supply voltage. The second network node includes a transmitter driving a differential voltage onto bus lines to communicate a dominant bus state at a second dominant state common mode voltage, a receiver coupled to the bus lines, sense circuitry to sense a common mode voltage at the bus lines, and control circuitry to control a recessive state common mode voltage in response to the sensed dominant state common mode voltage.
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Patent Agency Ranking
公开(公告)号：US12132481B2
公开(公告)日：2024-10-29
申请号：US17709734
申请日：2022-03-31
Applicant: Texas Instruments Incorporated
Inventor： Lokesh Kumar Gupta , Upasana Bhattacharya
IPC: H03K19/0948 , H03K3/0233 , H04L12/40
CPC classification number: H03K19/0948 , H03K3/02337 , H04L12/4013 , H04L2012/40215
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to buffer an input voltage. An example apparatus includes first inverter circuitry to invert the input voltage and produce a first inverted voltage; second inverter circuitry coupled to the first inverter circuitry, the second inverter circuitry to invert the first inverted voltage and produce a second inverted voltage at a rate based on a first current controlled transistor; third inverter circuitry coupled to the second inverter circuitry, the third inverter circuitry to invert the second inverted voltage and produce a third inverted voltage at a rate based on a second current controlled transistor; and fourth inverter circuitry coupled to the third inverter circuitry, the fourth inverter circuitry to invert the third inverted voltage and produce an output voltage, wherein the output voltage matches the input voltage.
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公开(公告)号：US20240146353A1
公开(公告)日：2024-05-02
申请号：US18081864
申请日：2022-12-15
Applicant: Texas Instruments Incorporated
Inventor： Ankita Paul , Lokesh Kumar Gupta
CPC classification number: H04B1/44 , G06F13/4072 , H03F3/45179 , H03F3/45668 , H04L12/40 , H04L2012/40215
Abstract: Differential signaling transmitter circuitry includes upper and lower driver stacks, each with at least one upper blocking transistor and a bias transistor, further includes first and second control loops. A first control loop includes a replica stack including replicas of the bias transistor and blocking transistors of a first one of the driver stacks, and a second control loop includes replica stacks, one with replicas of the bias and blocking transistors of the upper driver stack and one with replicas of the bias and blocking transistors of the lower driver stack. One of the replica stacks in the second control loop receives an output from the first control loop. First and second switching circuitry couples outputs of the first and second control loops to gates of bias transistor in the upper and lower driver stacks, respectively, responsive to a data signal.
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公开(公告)号：US10771280B1
公开(公告)日：2020-09-08
申请号：US16538975
申请日：2019-08-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Lokesh Kumar Gupta , Basant Bothra
Abstract: A system includes a controller area network (CAN) transceiver. The CAN transceiver includes a wake-up circuit having an attenuator circuit coupled to a CAN bus. The wake-up circuit also includes a common-gate amplifier circuit coupled to the attenuator circuit. The wake-up circuit also includes an offset generation circuit coupled to the common-gate amplifier circuit.
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公开(公告)号：US20180351765A1
公开(公告)日：2018-12-06
申请号：US15854583
申请日：2017-12-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Abhijeeth Aarey Premanath , Richard Edwin Hubbard , Maxwell Guy Robertson , Lokesh Kumar Gupta , Mark Edward Wentroble , Roland Sperlich , Dejan Radic
CPC classification number: H04L12/40032 , H04L12/12 , H04L12/40039 , H04L2012/40215 , H04L2012/40273
Abstract: Two CAN bus transceivers utilized in a single integrated circuit package with the CAN bus connections between the two transceivers being inverted. Thus, one transceiver is connected to the CAN bus high and low lines while the other transceiver is connected to the CAN bus low and high lines. Both transceivers power up in a standby condition and each transceiver is monitoring for wake up signals on the CAN bus. The transceiver that is correctly connected to the CAN bus detects wake up signals. When the wake up signals are detected at that transceiver, that transceiver is brought to full operating state and the other transceiver is placed in a full standby condition. Additional input resistance is provided with each transceiver to maintain the proper input resistance for the integrated circuit.
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公开(公告)号：US11870246B2
公开(公告)日：2024-01-09
申请号：US16411251
申请日：2019-05-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shishir Goyal , Lokesh Kumar Gupta
IPC: H02H9/04 , G01R19/10 , H02H1/00 , G01R19/165 , H03K17/082
CPC classification number: H02H9/045 , G01R19/10 , G01R19/16571 , H02H1/0007 , H03K17/0822 , H03K17/0826
Abstract: A positive overshoot detection circuit comprises a transistor coupled to a current mirror, a reference current source coupled to the current mirror, and a comparator coupled to the reference current source and the current mirror. The comparator output indicates whether the current mirror's current is greater than the reference current source's current. A control input and a current terminal of the transistor are coupled to a clamping circuit. A negative overshoot detection circuit comprises a biasing sub-circuit coupled to a transistor, a resistor coupled to the transistor, and a comparator coupled to the transistor and the resistor. The comparator output indicates whether the transistor is in an on or off state. The biasing sub-circuit is coupled to a clamping circuit. In some implementations, the comparator outputs from the positive and negative overshoot detection circuits are provided to a driver circuit, which modifies its operation.
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