-
公开(公告)号：US20210376718A1
公开(公告)日：2021-12-02
申请号：US16890537
申请日：2020-06-02
Applicant: Texas Instruments Incorporated
Inventor： Maik Peter Kaufmann , Michael Lueders , Bernhard Wicht
Abstract: Reference voltage generation circuits and related methods are disclosed. An example reference voltage generation circuit includes a voltage generating circuit including an enhancement mode (E-mode) gallium nitride (GaN) transistor, the voltage generating circuit to, in response to a first clock signal having a first phase, generate a first voltage associated with the E-mode GaN transistor, and, in response to a second clock signal having a second phase different from the first phase, generate a second voltage associated with the E-mode GaN transistor, and a switching capacitor circuit coupled to the voltage generating circuit, the switching capacitor circuit to generate a reference voltage based on a difference between the first voltage and the second voltage.
-
公开(公告)号：US20240313660A1
公开(公告)日：2024-09-19
申请号：US18141245
申请日：2023-04-28
Applicant: Texas Instruments Incorporated
Inventor： Laszlo Balogh , Michael Lueders , Stefan Herzer , Maik Peter Kaufmann
CPC classification number: H02M3/33576 , H02M1/0009 , H02M1/0025 , H02M1/36
Abstract: A self-biasing circuit for power converters is disclosed. In an example, an apparatus includes a first transistor coupled between an inductor terminal and a ground terminal, and a second transistor coupled between the inductor terminal and a bias terminal. The first transistor has a first control terminal, and the second transistor has a second control terminal. In an example, the first and second transistors are configured to split a current at the inductor terminal. The apparatus further includes a controller having first and second control outputs, where the first control output is coupled to the first control terminal, the second control output is coupled to the second control terminal.
-
公开(公告)号：US20220399328A1
公开(公告)日：2022-12-15
申请号：US17548426
申请日：2021-12-10
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Maik Peter Kaufmann , Michael Lueders , CHANG SOO SUH
IPC: H01L27/06 , H01L29/45 , H01L29/20 , H01L29/205 , H01L29/778 , H01L49/02 , H01L21/8252 , H01L29/66
Abstract: A depletion-mode current source having a saturation current of sufficient accuracy for use as a pre-charge circuit in a start-up circuit of an AC-to-DC power converter is fabricated using an enhancement-mode-only process. The depletion-mode current source can be fabricated on the same integrated circuit (IC) as a gallium nitride field-effect transistor (FET) and resistive and capacitive components used in the start-up circuit, without affecting the enhancement-mode-only fabrication process by requiring additional masks or materials, as would be required to fabricate a depletion-mode FET on the same IC as an enhancement-mode FET. The current source includes a resistive patterned two-dimensional electron gas (2DEG) or two-dimensional hole gas (2DHG) channel coupled between two terminals and one or more metal field plates extending from one of the terminals and overlying the patterned area of the channel, the field plates being separated from the channel and from each other by dielectric layers.
-
公开(公告)号：US11031933B2
公开(公告)日：2021-06-08
申请号：US16731847
申请日：2019-12-31
Applicant: Texas Instruments Incorporated
Inventor： Michael Lueders , Johan Strydom , Cetin Kaya , Maik Peter Kaufmann
Abstract: A startup circuit includes an enhancement mode transistor with a drain coupled to a startup circuit input, a source coupled to a first node, and a gate coupled to a second node. The startup circuit includes a current limiting circuit that controls a current path between the second node and a startup circuit output node based on a current sense voltage signal representing a current through the enhancement mode transistor, and a voltage regulation circuit controls a voltage of the second node to regulate a startup circuit output voltage of the startup circuit output node.
-
公开(公告)号：US12113062B2
公开(公告)日：2024-10-08
申请号：US17137784
申请日：2020-12-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Naveen Tipirneni , Maik Peter Kaufmann , Michael Lueders , Jungwoo Joh
IPC: H01L27/06 , H01L21/8252 , H01L29/20 , H01L29/66 , H01L29/778 , H01L49/02 , H02M3/156 , H03K3/037
CPC classification number: H01L27/0629 , H01L21/8252 , H01L27/0605 , H01L28/60 , H01L29/2003 , H01L29/66462 , H01L29/7781 , H02M3/156 , H03K3/0377
Abstract: The present invention provides a capacitor having a first structure made of a metal layer and a second structure made of the same metal layer and a dielectric layer between the first and the second metal structure, wherein the dielectric layer has a relative permittivity greater than 4, in particular greater than 6. It also provides a monolithically integrated circuit including such a capacitor and optionally other components. A method of manufacturing such a capacitor is also provided.
-
Patent Agency Ranking
公开(公告)号：US11621708B2
公开(公告)日：2023-04-04
申请号：US17314523
申请日：2021-05-07
Applicant: Texas Instruments Incorporated
Inventor： Michael Lueders , Johan Strydom , Cetin Kaya , Maik Peter Kaufmann
Abstract: A startup circuit adapted to be coupled to an input voltage supply and operable to supply an output voltage at an output terminal, the startup circuit including: a first transistor having a first control terminal, a first current terminal and a second current terminal, the first current terminal adapted to be coupled to the input voltage supply and the second current terminal coupled to the output terminal; a precharge circuit having a first terminal, a second terminal and a third terminal, the second terminal adapted to be coupled to the input voltage supply and the third terminal coupled to the first control terminal; a current limiter coupled to the precharge circuit, the first control terminal and the second current terminal; a second transistor having a second control terminal, a third current terminal and a fourth current terminal, the third current terminal coupled to the precharge circuit and the second control terminal adapted to be coupled to a control signal; and a third transistor having a third control terminal, a fifth current terminal and a sixth current terminal, the fifth current terminal coupled to the first control terminal and the third control terminal is adapted to be coupled to the control signal.
-
公开(公告)号：US20200274530A1
公开(公告)日：2020-08-27
申请号：US16731847
申请日：2019-12-31
Applicant: Texas Instruments Incorporated
Inventor： Michael Lueders , Johan Strydom , Cetin Kaya , Maik Peter Kaufmann
Abstract: A startup circuit includes an enhancement mode transistor with a drain coupled to a startup circuit input, a source coupled to a first node, and a gate coupled to a second node. The startup circuit includes a current limiting circuit that controls a current path between the second node and a startup circuit output node based on a current sense voltage signal representing a current through the enhancement mode transistor, and a voltage regulation circuit controls a voltage of the second node to regulate a startup circuit output voltage of the startup circuit output node.
-
公开(公告)号：US20250138567A1
公开(公告)日：2025-05-01
申请号：US18755318
申请日：2024-06-26
Applicant: Texas Instruments Incorporated
Inventor： Cetin Kaya , FNU Nitish , Maik Peter Kaufmann
IPC: G05F3/26 , H02P7/28 , H03K17/693
Abstract: An example apparatus includes: driver circuitry having a terminal; a capacitor having a terminal; diode circuitry having a first terminal and a second terminal; a transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the transistor coupled to the first terminal of the diode circuitry, the control terminal of the transistor coupled to the terminal of the capacitor and the second terminal of the diode circuitry; and current mirror circuitry having a first terminal and second terminal, the first terminal of the current mirror circuitry coupled to the terminal of the driver circuitry, the second terminal of the current mirror circuitry coupled to the second terminal of the transistor.
-
公开(公告)号：US20240429233A1
公开(公告)日：2024-12-26
申请号：US18828356
申请日：2024-09-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Naveen Tipirneni , Maik Peter Kaufmann , Michael Lueders , Jungwoo Joh
IPC: H01L27/06 , H01L21/8252 , H01L29/20 , H01L29/66 , H01L29/778 , H02M3/156 , H03K3/037
Abstract: The present invention provides a capacitor having a first structure made of a metal layer and a second structure made of the same metal layer and a dielectric layer between the first and the second metal structure, wherein the dielectric layer has a relative permittivity greater than 4, in particular greater than 6. It also provides a monolithically integrated circuit including such a capacitor and optionally other components. A method of manufacturing such a capacitor is also provided.
-
公开(公告)号：US20240146298A1
公开(公告)日：2024-05-02
申请号：US17977822
申请日：2022-10-31
Applicant: Texas Instruments Incorporated
Inventor： Raveesh Magod Ramakrishna , Maik Peter Kaufmann , Michael Lueders , Johan Strydom , Stefan Herzer
IPC: H03K17/687 , H03K5/13
CPC classification number: H03K17/6871 , H03K5/13 , H03K2005/00019
Abstract: In described examples, an integrated circuit includes first and second current sources, first and second switches, a dV/dt phase detector, a control circuit, and source, gate, and drain terminals for coupling to, respectively, a source, gate, and drain of a power FET. The first switch is coupled between the first current source and the gate terminal. The second switch is coupled between the second current source and the gate terminal. The dV/dt phase detector detects a dV/dt phase of the power FET and outputs to the control circuit. The control circuit controls the first and second switches to perform a turn-on sequence of the power FET, including: closing the first switch while keeping the second switch open; and after receiving a signal from the dV/dt phase detector indicating the dV/dt phase has started, opening the first switch, and closing the second switch.
-
-
-
-
-
-
-
-
-
Search Results
14
records
(took 0.013 seconds)
