公开(公告)号：US12113062B2

公开(公告)日：2024-10-08

申请号：US17137784

申请日：2020-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Tipirneni ,  Maik Peter Kaufmann ,  Michael Lueders ,  Jungwoo Joh

IPC: H01L27/06 ,  H01L21/8252 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H01L49/02 ,  H02M3/156 ,  H03K3/037

CPC classification number: H01L27/0629 ,  H01L21/8252 ,  H01L27/0605 ,  H01L28/60 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7781 ,  H02M3/156 ,  H03K3/0377

Abstract: The present invention provides a capacitor having a first structure made of a metal layer and a second structure made of the same metal layer and a dielectric layer between the first and the second metal structure, wherein the dielectric layer has a relative permittivity greater than 4, in particular greater than 6. It also provides a monolithically integrated circuit including such a capacitor and optionally other components. A method of manufacturing such a capacitor is also provided.

公开(公告)号：US11049960B2

公开(公告)日：2021-06-29

申请号：US16294687

申请日：2019-03-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chang Soo Suh ,  Sameer Prakash Pendharkar ,  Naveen Tipirneni ,  Jungwoo Joh

IPC: H01L29/872 ,  H01L29/205 ,  H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L21/308 ,  H01L29/417 ,  H01L21/02

Abstract: In some examples, a gallium nitride (GaN)-based transistor, comprises a substrate; a GaN layer supported by the substrate; an aluminum nitride gallium (AlGaN) layer supported by the GaN layer; a p-doped GaN structure supported by the AlGaN layer; and multiple p-doped GaN blocks supported by the AlGaN layer, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers.

公开(公告)号：US10707324B2

公开(公告)日：2020-07-07

申请号：US16456040

申请日：2019-06-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chang Soo Suh ,  Dong Seup Lee ,  Jungwoo Joh ,  Naveen Tipirneni ,  Sameer Prakash Pendharkar

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/10 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/085 ,  H01L23/535 ,  H01L29/20 ,  H01L27/07 ,  H01L27/088

Abstract: One example provides an enhancement-mode High Electron Mobility Transistor (HEMT) includes a substrate, a Group IIIA-N active layer over the substrate, a Group IIIA-N barrier layer over the active layer, and at least one isolation region through the barrier layer to provide an isolated active area having the barrier layer on the active layer. A gate stack is located between source and drain contacts to the active layer. A tunnel diode in the gate stack includes an n-GaN layer on an InGaN layer on a p-GaN layer located on the barrier layer.

公开(公告)号：US20240429233A1

公开(公告)日：2024-12-26

申请号：US18828356

申请日：2024-09-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Tipirneni ,  Maik Peter Kaufmann ,  Michael Lueders ,  Jungwoo Joh

IPC: H01L27/06 ,  H01L21/8252 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H02M3/156 ,  H03K3/037

Abstract: The present invention provides a capacitor having a first structure made of a metal layer and a second structure made of the same metal layer and a dielectric layer between the first and the second metal structure, wherein the dielectric layer has a relative permittivity greater than 4, in particular greater than 6. It also provides a monolithically integrated circuit including such a capacitor and optionally other components. A method of manufacturing such a capacitor is also provided.

公开(公告)号：US20220208755A1

公开(公告)日：2022-06-30

申请号：US17137784

申请日：2020-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Tipirneni ,  Maik Peter Kaufmann ,  Michael Lueders ,  Jungwoo Joh

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/20 ,  H01L29/778 ,  H01L21/8252 ,  H01L29/66

Abstract: The present invention provides a capacitor having a first structure made of a metal layer and a second structure made of the same metal layer and a dielectric layer between the first and the second metal structure, wherein the dielectric layer has a relative permittivity greater than 4, in particular greater than 6. It also provides a monolithically integrated circuit including such a capacitor and optionally other components. A method of manufacturing such a capacitor is also provided.

公开(公告)号：US20170148905A1

公开(公告)日：2017-05-25

申请号：US14951927

申请日：2015-11-25

Applicant: Texas Instruments Incorporated

Inventor： Naveen Tipirneni ,  Sameer Pendharkar

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L29/778 ,  H01L21/7605 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device with a substrate, a low defect layer formed in a fixed position relative to the substrate, and a barrier layer comprising III-N semiconductor material formed on the low-defect layer and forming an electron gas in the low-defect layer. The device also has a source contact, a drain contact, and a gate contact for receiving a potential, the potential for adjusting a conductive path in the electron gas and between the source contact and the drain contact. Lastly, the device has a one-sided PN junction between the barrier layer and the substrate.

公开(公告)号：US09543944B2

公开(公告)日：2017-01-10

申请号：US15168458

申请日：2016-05-31

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Naveen Tipirneni

IPC: H03K17/687 ,  H01L29/20 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L27/092 ,  H03F3/193 ,  H03F3/195 ,  H02M5/257

CPC classification number: H03K17/6872 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/8236 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0883 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/7833 ,  H02M5/2573 ,  H03F3/193 ,  H03F3/195 ,  H03K17/6871 ,  H03K17/6877 ,  H03K2017/6875

Abstract: A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode cascoded NMOS transistor which is connected in series to a source node of the GaN FET. The integrated driver/cascode IC further includes a driver circuit which conditions a gate input signal and provides a suitable digital waveform to a gate node of the cascoded NMOS transistor. The cascoded NMOS transistor and the driver circuit are formed on a same silicon substrate.

Abstract translation: 半导体器件包括耗尽型GaN FET和集成驱动器/共源共栅IC。 集成驱动器/共源共极集成电路包括与GaN FET的源极节点串联连接的增强型共模NMOS晶体管。 集成驱动器/共源共极IC还包括驱动电路，其调节栅极输入信号并向级联的NMOS晶体管的栅极节点提供合适的数字波形。 级联的NMOS晶体管和驱动电路形成在相同的硅衬底上。

公开(公告)号：US09396948B2

公开(公告)日：2016-07-19

申请号：US13886652

申请日：2013-05-03

Applicant: Texas Instruments Incorporated

Inventor： Naveen Tipirneni ,  Sameer Pendharkar ,  Rick L. Wise

IPC: H01L21/34 ,  H01L21/18 ,  H01L21/762 ,  H01L21/8258

CPC classification number: H01L21/187 ,  H01L21/76254 ,  H01L21/8258

Abstract: An integrated silicon and III-N semiconductor device may be formed by growing III-N semiconductor material on a first silicon substrate having a first orientation. A second silicon substrate with a second, different, orientation has a release layer between a silicon device film and a carrier wafer. The silicon device film is attached to the III-N semiconductor material while the silicon device film is connected to the carrier wafer through the release layer. The carrier wafer is subsequently removed from the silicon device film. A first plurality of components is formed in and/or on the silicon device film. A second plurality of components is formed in and/or on III-N semiconductor material in the exposed region. In an alternate process, a dielectric interlayer may be disposed between the silicon device film and the III-N semiconductor material in the integrated silicon and III-N semiconductor device.

Abstract translation: 可以通过在具有第一取向的第一硅衬底上生长III-N半导体材料来形成集成的硅和III-N半导体器件。 具有第二不同取向的第二硅衬底在硅器件膜和载体晶片之间具有释放层。 硅器件膜附着到III-N半导体材料上，而硅器件膜通过释放层连接到载体晶片。 随后从硅器件膜移除载体晶片。 在硅器件膜上和/或上形成第一多个部件。 在暴露区域中的III-N半导体材料中和/或上形成第二组分。 在替代方法中，可以在集成硅和III-N半导体器件中的硅器件膜和III-N半导体材料之间设置电介质中间层。

公开(公告)号：US09379022B2

公开(公告)日：2016-06-28

申请号：US14745749

申请日：2015-06-22

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Naveen Tipirneni

IPC: H01L21/8236 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/06 ,  H01L29/16 ,  H01L29/20

CPC classification number: H03K17/6872 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/8236 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0883 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/7833 ,  H02M5/2573 ,  H03F3/193 ,  H03F3/195 ,  H03K17/6871 ,  H03K17/6877 ,  H03K2017/6875

Abstract: A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode cascoded NMOS transistor which is connected in series to a source node of the GaN FET. The integrated driver/cascode IC further includes a driver circuit which conditions a gate input signal and provides a suitable digital waveform to a gate node of the cascoded NMOS transistor. The cascoded NMOS transistor and the driver circuit are formed on a same silicon substrate.

Abstract translation: 半导体器件包括耗尽型GaN FET和集成驱动器/共源共栅IC。 集成驱动器/共源共极集成电路包括与GaN FET的源极节点串联连接的增强型共模NMOS晶体管。 集成驱动器/共源共极IC还包括驱动电路，其调节栅极输入信号并向级联的NMOS晶体管的栅极节点提供合适的数字波形。 级联的NMOS晶体管和驱动电路形成在相同的硅衬底上。

公开(公告)号：US09196692B2

公开(公告)日：2015-11-24

申请号：US14706595

申请日：2015-05-07

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Naveen Tipirneni

IPC: H01L23/58 ,  H01L29/40 ,  H01L21/311 ,  H01L29/417 ,  H01L29/66 ,  H01L29/812 ,  H01L29/20 ,  H01L29/78

CPC classification number: H01L29/404 ,  H01L21/31144 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66871 ,  H01L29/78 ,  H01L29/812

Abstract: A semiconductor device is formed with a stepped field plate over at least three sequential regions in which a total dielectric thickness under the stepped field plate is at least 10 percent thicker in each region compared to the preceding region. The total dielectric thickness in each region is uniform. The stepped field plate is formed over at least two dielectric layers, of which at least all but one dielectric layer is patterned so that at least a portion of a patterned dielectric layer is removed in one or more regions of the stepped field plate.