公开(公告)号：US10915121B2

公开(公告)日：2021-02-09

申请号：US16184414

申请日：2018-11-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raveesh Magod Ramakrishna ,  Sanjeev Manandhar

IPC: G05F1/565

Abstract: A system includes a low dropout regulator (LDO) circuit. The LDO circuit includes an error amplifier with an input node, a reference node, and an output node. The LDO circuit also includes a pass transistor with a control terminal, a first current terminal, and a second current terminal. The control terminal is coupled to the output node of the error amplifier, the first current terminal is coupled to a voltage source node, and the second current terminal is coupled to an LDO output node. The LDO output node is coupled to the input node of the error amplifier. The LDO circuit also includes a switched-capacitor network coupled between error amplifier and the pass transistor. The switched-capacitor network comprises a pair of switches and a current-controlled oscillator coupled to control terminals of the switches.

公开(公告)号：US10826465B2

公开(公告)日：2020-11-03

申请号：US16742030

申请日：2020-01-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raveesh Magod Ramakrishna

IPC: H03K3/0231 ,  H03K3/011 ,  H03K3/012 ,  H03K3/017

Abstract: A device includes a capacitor having a first terminal coupled to a ground node, and a second terminal; a first transistor having a source coupled to the capacitor, a drain coupled to a first node, and a gate; a first current source coupled to the first node and configured to couple to a regulated supply node; a second transistor having a source coupled to the ground node, a drain coupled to a second node, and a gate coupled to the second node and to the gate of the first transistor; and a comparator circuit having an input coupled to the first node and an output configured to couple to a clock node.

公开(公告)号：US11435771B2

公开(公告)日：2022-09-06

申请号：US16810108

申请日：2020-03-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Alan Sankman ,  Raveesh Magod Ramakrishna

IPC: G05F1/575 ,  G05F1/59

Abstract: A system includes a battery. The system also includes a low dropout regulator (LDO) circuit with an input coupled to the battery and the LDO circuit. The system also includes a load coupled to an output of the LDO circuit. The LDO circuit includes an error amplifier and a control circuit coupled to the error amplifier. The LDO circuit also includes a first pass transistor coupled to the control circuit and configured to provide a first pass current as a function of load current according to a first continuous conduction curve. The LDO circuit also includes a second pass transistor coupled to the control circuit and configured to provide a second pass current as a function of load current according to a second continuous conduction curve.

公开(公告)号：US20240146298A1

公开(公告)日：2024-05-02

申请号：US17977822

申请日：2022-10-31

Applicant: Texas Instruments Incorporated

Inventor： Raveesh Magod Ramakrishna ,  Maik Peter Kaufmann ,  Michael Lueders ,  Johan Strydom ,  Stefan Herzer

IPC: H03K17/687 ,  H03K5/13

CPC classification number: H03K17/6871 ,  H03K5/13 ,  H03K2005/00019

Abstract: In described examples, an integrated circuit includes first and second current sources, first and second switches, a dV/dt phase detector, a control circuit, and source, gate, and drain terminals for coupling to, respectively, a source, gate, and drain of a power FET. The first switch is coupled between the first current source and the gate terminal. The second switch is coupled between the second current source and the gate terminal. The dV/dt phase detector detects a dV/dt phase of the power FET and outputs to the control circuit. The control circuit controls the first and second switches to perform a turn-on sequence of the power FET, including: closing the first switch while keeping the second switch open; and after receiving a signal from the dV/dt phase detector indicating the dV/dt phase has started, opening the first switch, and closing the second switch.