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公开(公告)号:US20240213178A1
公开(公告)日:2024-06-27
申请号:US18595905
申请日:2024-03-05
Applicant: Texas Instruments Incorporated
Inventor: Tomoko NOGUCHI , Mutsumi MASUMOTO , Kengo AOYA , Masamitsu MATSUURA
IPC: H01L23/552 , H01L21/56 , H01L21/683 , H01L21/78 , H01L23/00 , H01L23/31 , H01L23/498
CPC classification number: H01L23/552 , H01L21/561 , H01L21/6836 , H01L21/78 , H01L23/3114 , H01L23/3135 , H01L23/49816 , H01L24/48 , H01L2224/48245
Abstract: A semiconductor device includes a semiconductor die having a top side surface comprising a semiconductor material including circuitry therein having bond pads connected to nodes in the circuitry, a bottom side surface, and sidewall surfaces between the top side surface and the bottom side surface. A metal coating layer including a bottom side metal layer is over the bottom side surface that extends continuously to a sidewall metal layer on the sidewall surfaces. The sidewall metal layer defines a sidewall plane that is at an angle from 10° to 60° relative to a normal projected from a bottom plane defined by the bottom side metal layer.
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公开(公告)号:US20220208689A1
公开(公告)日:2022-06-30
申请号:US17139417
申请日:2020-12-31
Applicant: Texas Instruments Incorporated
Inventor: Tomoko NOGUCHI , Mutsumi MASUMOTO , Kengo AOYA , Masamitsu MATSUURA
IPC: H01L23/552 , H01L23/31 , H01L23/00 , H01L23/498 , H01L21/78 , H01L21/56 , H01L21/683
Abstract: A semiconductor device includes a semiconductor die having a top side surface comprising a semiconductor material including circuitry therein having bond pads connected to nodes in the circuitry, a bottom side surface, and sidewall surfaces between the top side surface and the bottom side surface. A metal coating layer including a bottom side metal layer is over the bottom side surface that extends continuously to a sidewall metal layer on the sidewall surfaces. The sidewall metal layer defines a sidewall plane that is at an angle from 10° to 60° relative to a normal projected from a bottom plane defined by the bottom side metal layer.
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公开(公告)号:US20210125959A1
公开(公告)日:2021-04-29
申请号:US16663089
申请日:2019-10-24
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Masamitsu MATSUURA , Kengo AOYA , Mutsumi MASUMOTO
IPC: H01L23/00 , H01L23/552 , H01L21/683 , H01L21/78
Abstract: In some examples, a wafer chip scale package (WCSP) comprises a die; multiple electrically conductive terminals coupled to a first surface of the die; and a metal covering abutting five surfaces of the die besides the first surface, each of the five surfaces of the die lying in a different plane.
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